6.5.1 Predicted and non-predicted instructions

This section describes the instructions that the processor predicts.

Unless otherwise specified, the list applies to A32, T32, and A64 instructions. As a general rule, the branch prediction hardware predicts all branch instructions regardless of the addressing mode, including:
  • Conditional branches.
  • Unconditional branches.
  • Indirect branches.
  • Branches that switch between ARM and Thumb states.
  • PC destination data processing operations.
  • BXJ, because of the inclusion of the trivial Jazelle implementation, this degenerates to a BX instruction. There is no BXJ instruction in A64.
However, the following branch instructions are not predicted:
  • AArch32 instructions with the S suffix are not predicted because they are typically used when returning from exceptions and have side effects that can change privilege mode and Security state.
  • All mode or Exception level changing instructions.
In Thumb state, you can make a branch that is normally encoded as unconditional conditional by including an If-Then (IT) block. It is then treated as a normal conditional branch.
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