6.6 L1 RAM memories

The L1 memory system contains several RAM memories that can be configured to use ECC or parity error detection mechanisms.

Any RAM memory that uses ECC support can perform single bit error correction and double bit error detection. Contents of the RAM memories with parity support can invalidate entries if a parity error is detected because this data is associated with read-only structures.
The following table shows all RAM memories contained in the L1 memory system.

Table 6-2 L1 RAM memories

RAM memory ECC or Parity
L1 instruction Tag RAM Parity
L1 instruction Data RAM Parity
L1 instruction BTB RAM None
L1 instruction GHB RAM None
L1 instruction indirect predictor RAM None
L1 data Tag RAM ECC
L1 Data RAM ECC
L1 PF PHT RAM None
L2 TLB RAMa Parity
a The L2 TLB RAM is a unified TLB structure that supports L1 instruction and L1 data TLB misses.
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