8.1 About the GIC

The GIC is a resource for supporting and managing interrupts in a cluster system.

It implements the GIC CPU interface and provides:
  • Registers for managing:
    • Interrupt sources.
    • Interrupt behavior.
    • Interrupt routing to one or more processors.
The GIC supports:
  • Two Security states.
  • Interrupt virtualization.
  • Software-generated Interrupts (SGIs).
  • System Error Interrupts (SEIs).
  • Message-based interrupts.
  • System register access.
  • Memory-mapped register access.
  • Interrupt masking and prioritization.
  • Interrupt routing based on processor affinity, in multiprocessor environments.
  • Interrupt routing based on specifying target processors.
  • Wake-up events in power-management environments.
The GIC includes interrupt grouping functionality that supports:
  • Configuring each interrupt to belong to an interrupt group.
  • Signaling Group 1 interrupts to the target processor using either the IRQ or the FIQ exception request.
  • Signaling Group 0 interrupts to the target processor using the FIQ exception request only.
  • A unified scheme for handling the priority of Group 0 and Group 1 interrupts.
The Cortex-A72 processor implements the GIC CPU interface as described in the Generic Interrupt Controller (GICv3) architecture. It can interface with a GICv3 Distributor component in the system.
This chapter only describes features that are specific to the Cortex-A72 processor implementation.
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