GICv3 interrupt messages that are sent by an external Distributor. Each interrupt
message has a unique interrupt ID.
| Local Peripheral Interrupts (LPIs) | An interrupt generated by a peripheral that is destined for one or more
processors within a specific affinity hierarchy. |
| Private Peripheral Interrupts (PPIs) | An interrupt generated by a peripheral that is specific to a single processor.
All PPIs must connect directly to the external Distributor. |
| Shared Peripheral Interrupts (SPIs). | An interrupt generated by a peripheral that is destined for one or more
processors. All SPIs must connect directly to the external Distributor. |
| Software Generated Interrupts (SGIs) | SGIs are generated by:
- Writing to the ICC_SGI0R, ICC_SGI1R, or ICC_ASGI1R registers in the CPU
interface when in System-register mode.
- Writing to the Software Generated Interrupt Register, GICD_SGIR, in the
external Distributor when in memory-mapped mode.
A maximum of 16 SGIs, ID0-ID15, can be generated for each processor interface.
An SGI has edge-triggered properties. The software triggering of the interrupt
is equivalent to the edge transition of the interrupt signal on a peripheral
input.
|
| System Error Interrupts (SEIs) | System Errors can be generated internally using the nSEI, nVSEI, or nREI signals.
See the ARM® Generic Interrupt Controller Architecture
Specification, GICv3 for more information. |
| Virtual Local Peripheral Interrupts (vLPIs) | A virtual interrupt generated by a write to the Distributor that is destined for
one or more processors within a specific affinity hierarchy. See the ARM® Generic Interrupt Controller Architecture Specification,
GICv3 for more information. |
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