9.2 Generic Timer functional description

The Cortex-A72 processor provides a set of timers for each core in the processor.

The timers are:
  • A Non-secure EL1 physical timer.
  • A Secure EL1 physical timer.
  • A Non-secure EL2 physical timer.
  • A virtual timer.
The processor does not include the system counter that resides in the SoC. The system counter value is distributed to the Cortex-A72 processor with a synchronous binary encoded 64-bit bus, CNTVALUEB[63:0].
Because CNTVALUEB is generated from a system counter that typically operates at a slower frequency than the main processor CLK, the CNTCLKEN input is provided as a clock enable for the CNTVALUEB bus.
Each timer provides an active-LOW interrupt output that is an external pin to the SoC.
The following table shows the signals that are the external interrupt output pins.

Table 9-1 Generic Timer signals

Signala Description
nCNTPNSIRQ[n:0] Non-secure EL1 physical timer interrupt
nCNTPSIRQ[n:0] Secure EL1 physical timer interrupt
nCNTHPIRQ[n:0] Non-secure EL2 physical timer interrupt
nCNTVIRQ[n:0] Virtual timer interrupt
Related information
2.3.1 Clocks
a n is the number of processors present in the MPCore device, minus one.
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