9.3.2 AArch32 Generic Timer register summary

The following table shows the AArch32 Generic Timer registers.

See the ARM® Architecture Reference Manual ARMv8 for information about these registers.

Table 9-3 AArch32 Generic Timer registers

Name CRn op1 CRm op2 Type Reset Width Description
CNTFRQ c14 0 c0 0 RW a UNK 32-bit Timer Counter Frequency register
CNTPCT - 0 c14 - RO UNK 64-bit Physical Timer Count register
CNTKCTL c14 0 c1 0 RW -b 32-bit EL1 Timer Control register
CNTP_TVAL     c2 0 RW UNK 32-bit EL1 Physical Timer TimerValue register
CNTP_CTL       1 RW
-c
32-bit EL1 Physical Timer Control register
CNTV_TVAL     c3 0 RW UNK 32-bit Virtual Timer TimerValue register
CNTV_CTL       1 RW c 32-bit Virtual Timer Control register
CNTVCT - 1 c14 - RO UNK 64-bit Virtual Timer Count register
CNTP_CVAL   2     RW UNK 64-bit EL1 Physical Timer CompareValue register
CNTV_CVAL   3     RW UNK 64-bit Virtual Timer CompareValue register
CNTVOFF   4     RW UNK 64-bit Virtual Timer Offset register
CNTHCTL c14 4 c1 0 RW
-d
32-bit EL2 Timer Control register
CNTHP_TVAL     c2 0 RW UNK 32-bit EL2 Physical Timer TimerValue register
CNTHP_CTL       1 RW c 32-bit EL2 Physical Timer Control register
CNTHP_CVAL - 6 c14 - RW UNK 64-bit EL2 Physical Timer CompareValue register
a Only at EL3, otherwise this register is RO.
b The reset value for bits[9:8, 2:0] is 0b00000.
c 
The reset value for bit[0] is 0.
d The reset value for bit[2] is 0 and for bits[1:0] is 0b11.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.