10.3 AArch64 debug register summary

Provides a summary of the debug control registers in the AArch64 state.

The following table shows the debug control registers that are accessible in AArch64 state. These registers are accessed by the MRS and MSR instructions.
The table also shows the offset address for the AArch64 registers that are accessible from the internal memory-mapped interface or the external debug interface. See 10.7 Memory-mapped register summary for a complete list of registers accessible from the internal memory-mapped or the external debug interface.

Table 10-3 AArch64 debug register summary

Offset Name Type Width Description
- DBGDTR_EL0 RW 64-bit Debug Data Transfer Register, half-duplex a
- DBGVCR32_EL2 RW 32-bit Debug Vector Catch Register a
- MDCCINT_EL1 RW 32-bit Monitor Debug Comms Channel Interrupt Enable Register a
- MDCCSR_EL0 RO 32-bit Monitor Debug Comms Channel Status Register a
- MDRAR_EL1 RO 64-bit Monitor Debug ROM Address Register a
- MDSCR_EL1 RW 32-bit Monitor Debug System Control Register a
- OSDTRRX_EL1 RW 32-bit OS Lock Data Transfer Register, Receive, External View 
- OSDTRTX_EL1 RW 32-bit OS Lock Data Transfer Register, Transmit, External View a
- OSDLR_EL1 RW 32-bit OS Double Lock Register a
- OSLSR_EL1 RO 32-bit OS Lock Status Register
0x080 DBGDTRRX_EL0 RO 32-bit Debug Data Transfer Register, Receive, Internal View a
0x08C DBGDTRTX_EL0 WO 32-bit Debug Data Transfer Register, Transmit, Internal View a
0x098 OSECCR_EL1 RW 32-bit OS Lock Exception Catch Control Register a
0x300 OSLAR_EL1 WO 32-bit Debug OS Lock Access Register a
0x310 DBGPRCR_EL1 RW 32-bit Debug Power/Reset Control Register a
0x400 DBGBVR0_EL1 RW 64-bit Debug Breakpoint Value Register 0 a
0x408 DBGBCR0_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x410 DBGBVR1_EL1 RW 64-bit Debug Breakpoint Value Register 1 a
0x418 DBGBCR1_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x420 DBGBVR2_EL1 RW 64-bit Debug Breakpoint Value Register 2 a
0x428 DBGBCR2_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x430 DBGBVR3_EL1 RW 64-bit Debug Breakpoint Value Register 3 a
0x438 DBGBCR3_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x440 DBGBVR4_EL1 RW 64-bit Debug Breakpoint Value Register 4 a
0x448 DBGBCR4_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x450 DBGBVR5_EL1 RW 64-bit Debug Breakpoint Value Register 5 a
0x458 DBGBCR5_EL1 RW 32-bit 10.4.1 Debug Breakpoint Control Registers, EL1
0x800 DBGWVR0_EL1 RW 64-bit Debug Watchpoint Value Register 0 a
0x808 DBGWCR0_EL1 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
0x810 DBGWVR1_EL1 RW 64-bit Debug Watchpoint Value Register 1 a
0x818 DBGWCR1_EL1 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
0x820 DBGWVR2_EL1 RW 64-bit Debug Watchpoint Value Register 2 a
0x828 DBGWCR2_EL1 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
0x830 DBGWVR3_EL1 RW 64-bit Debug Watchpoint Value Register 3 a
0x838 DBGWCR3_EL1 RW 32-bit 10.4.2 Debug Watchpoint Control Registers, EL1
0xFA0 DBGCLAIMSET_EL1 RW 32-bit Debug Claim Tag Set Register a
0xFA4 DBGCLAIMCLR_EL1 RW 32-bit Debug Claim Tag Clear Register a
0xFB8 DBGAUTHSTATUS_EL1 RO 32-bit Debug Authentication Status Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
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