10.6.2 Debug Device ID Register 1

The DBGDEVID1 characteristics are:
Adds to the information given by the DBGDIDR by describing other features of the debug implementation.
Usage constraints
The accessibility to the DBGDEVID1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The DBGDEVID1 is Common to Secure and Non-secure states.
See the register summary in Table 10-6 AArch32 debug register summary.
The following figure shows the DBGDEVID1 bit assignments.
Figure 10-5 DBGDEVID1 bit assignments
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The following table shows the DBGDEVID1 bit assignments.

Table 10-8 DBGDEVID1 bit assignments

Bits Name Function
[31:4] - Reserved, RES0.
[3:0] PCSROffset
Indicates the offset applied to PC samples returned by reads of EDPCSR. The value is:
0x2EDPCSR samples have no offset applied and do not sample the instruction set state in the AArch32 state.
To access the DBGDEVID1 in AArch32 state, read the CP14 register with:
MRC p14, 0, <Rt>, c7, c1, 47 Read Debug Device ID Register 1
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