ARM Cortex-A72 MPCore Processor Technical Reference Manual : 10.7 Memory-mapped register summary

10.7 Memory-mapped register summary

The following table shows the offset address for the registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 10-10 Memory-mapped debug register summary

Offset	Name	Type	Width	Description
`0x000`-`0x01C`	-	-	-	Reserved
`0x020`	EDESR	RW	32-bit	External Debug Event Status Register
`0x024`	EDECR	RW	32-bit	External Debug Execution Control Register ^a
`0x028`-`0x02C`	-	-	-	Reserved
`0x030`	EDWARlo	RO	32-bit	External Debug Watchpoint Address Register, low word ^a
`0x034`	EDWARhi	RO	32-bit	External Debug Watchpoint Address Register, high word ^a
`0x038`-`0x07C`	-	-	-	Reserved
`0x080`	DBGDTRRX_EL0	RW	32-bit	Debug Data Transfer Register, Receive ^a
`0x084`	EDITR	WO	32-bit	External Debug Instruction Transfer Register ^a
`0x088`	EDSCR	RW	32-bit	External Debug Status and Control Register ^a
`0x08C`	DBGDTRTX_EL0	RW	32-bit	Debug Data Transfer Register, Transmit ^a
`0x090`	EDRCR	WO	32-bit	External Debug Reserve Control Register ^a
`0x094`	EDACR	RW	32-bit	10.8.2 External Debug Auxiliary Control Register.
`0x098`	EDECCR	RW	32-bit	External Debug Exception Catch Control Register ^a
`0x09C`	-	-	-	Reserved
`0x0A0`	EDPCSRlo	RO	32-bit	External Debug Program Counter Sample Register, low word ^a
`0x0A4`	EDCIDSR	RO	32-bit	External Debug Context ID Sample Register ^a
`0x0A8`	EDVIDSR	RO	32-bit	External Debug Virtual Context Sample Register ^a
`0x0AC`	EDPCSRhi	RO	32-bit	External Debug Program Counter Sample Register, high word ^a
`0x0B0`-`0x2FC`	-	-	-	Reserved
`0x300`	OSLAR_EL1	WO	32-bit	Debug OS Lock Access Register ^a
`0x304`-`0x30C`	-	-	-	Reserved
`0x310`	EDPRCR	RW	32-bit	External Debug Power/Reset Control Register ^a
`0x314`	EDPRSR	RO	32-bit	External Debug Processor Status Register ^a
`0x318`-`0x3FC`	-	-	-	Reserved
`0x400`	DBGBVR0_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 0 ^a
`0x404`	DBGBVR0_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 0 ^a
`0x408`	DBGBCR0_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x40C`	-	-	-	Reserved
`0x410`	DBGBVR1_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 1 ^a
`0x414`	DBGBVR1_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 1 ^a
`0x418`	DBGBCR1_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x41C`	-	-	-	Reserved
`0x420`	DBGBVR2_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 2 ^a
`0x424`	DBGBVR2_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 2 ^a
`0x428`	DBGBCR2_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x42C`	-	-	-	Reserved
`0x430`	DBGBVR3_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 3 ^a
`0x434`	DBGBVR3_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 3 ^a
`0x438`	DBGBCR3_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x43C`	-	-	-	Reserved
`0x440`	DBGBVR4_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 4 ^a
`0x444`	DBGBVR4_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 4 ^a
`0x448`	DBGBCR4_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x44C`	-	-	-	Reserved
`0x450`	DBGBVR5_EL1[31:0]	RW	32-bit	Debug Breakpoint Value Register 5 ^a
`0x454`	DBGBVR5_EL1[63:32]	RW	32-bit	Debug Breakpoint Value Register 5 ^a
`0x458`	DBGBCR5_EL1	RW	32-bit	10.4.1 Debug Breakpoint Control Registers, EL1
`0x45C`-`0x7FC`	-	-	-	Reserved
`0x800`	DBGWVR0_EL1[31:0]	RW	32-bit	Debug Watchpoint Value Register 0 ^a
`0x804`	DBGWVR0_EL1[63:32]	RW	32-bit	Debug Watchpoint Value Register 0 ^a
`0x808`	DBGWCR0_EL1	RW	32-bit	10.4.2 Debug Watchpoint Control Registers, EL1
`0x80C`	-	-	-	Reserved
`0x810`	DBGWVR1_EL1[31:0]	RW	32-bit	Debug Watchpoint Value Register 1 ^a
`0x814`	DBGWVR1_EL1[63:32]	RW	32-bit	Debug Watchpoint Value Register 1 ^a
`0x818`	DBGWCR1_EL1	RW	32-bit	10.4.2 Debug Watchpoint Control Registers, EL1
`0x81C`	-	-	-	Reserved
`0x820`	DBGWVR2_EL1[31:0]	RW	32-bit	Debug Watchpoint Value Register 2 ^a
`0x824`	DBGWVR2_EL1[63:32]	RW	32-bit	Debug Watchpoint Value Register 2 ^a
`0x828`	DBGWCR2_EL1	RW	32-bit	10.4.2 Debug Watchpoint Control Registers, EL1
`0x82C`	-	-	-	Reserved
`0x830`	DBGWVR3_EL1[31:0]	RW	32-bit	Debug Watchpoint Value Register 3 ^a
`0x834`	DBGWVR3_EL1[63:32]	RW	32-bit	Debug Watchpoint Value Register 3 ^a
`0x838`	DBGWCR3_EL1	RW	32-bit	10.4.2 Debug Watchpoint Control Registers, EL1
`0x83C`-`0xCFC`	-	-	-	Reserved
`0xD00`	MIDR_EL1	RO	32-bit	4.3.1 Main ID Register, EL1
`0xD04`-`0xD1C`	-	-	-	Reserved
`0xD20`	ID_AA64PFR0_EL1[31:0]	RO	32-bit	4.3.18 AArch64 Processor Feature Register 0, EL1
`0xD24`	ID_AA64PFR0_EL1[63:32]	RO	32-bit	4.3.18 AArch64 Processor Feature Register 0, EL1
`0xD28`	ID_AA64DFR0_EL1[31:0]	RO	32-bit	4.3.19 AArch64 Debug Feature Register 0, EL1
`0xD2C`	ID_AA64DFR0_EL1[63:32]	RO	32-bit	4.3.19 AArch64 Debug Feature Register 0, EL1
`0xD30`	ID_AA64ISAR0_EL1[31:0]	RO	32-bit	4.3.20 AArch64 Instruction Set Attribute Register 0, EL1
`0xD34`	ID_AA64ISAR0_EL1[63:32]	RO	32-bit	4.3.20 AArch64 Instruction Set Attribute Register 0, EL1
`0xD38`	ID_AA64MMFR0_EL1[31:0]	RO	32-bit	4.3.21 AArch64 Memory Model Feature Register 0, EL1
`0xD3C`	ID_AA64MMFR0_EL1[63:32]	RO	32-bit	4.3.21 AArch64 Memory Model Feature Register 0, EL1
`0xD40`	ID_AA64PFR1_EL1[31:0]	RO	32-bit	AArch64 Processor Feature Register 1 low word, RES0
`0xD44`	ID_AA64PFR1_EL1[63:32]	RO	32-bit	AArch64 Processor Feature Register 1 high word, RES0
`0xD48`	ID_AA64DFR1_EL1[31:0]	RO	32-bit	AArch64 Debug Feature Register 1 low word, RES0
`0xD4C`	ID_AA64DFR1_EL1[63:32]	RO	32-bit	AArch64 Debug Feature Register 1 high word, RES0
`0xD50`	ID_AA64ISAR1_EL1[31:0]	RO	32-bit	AArch64 Instruction Set Attribute Register 1 low word, RES0
`0xD54`	ID_AA64ISAR1_EL1[63:32]	RO	32-bit	AArch64 Instruction Set Attribute Register 1 high word, RES0
`0xD58`	ID_AA64MMFR1_EL1[31:0]	RO	32-bit	AArch64 Memory Model Feature Register 1 low word, RES0
`0xD5C`	ID_AA64MMFR1_EL1[63:32]	RO	32-bit	AArch64 Memory Model Feature Register 1 high word, RES0
`0xD60`-`0xEF4`	-	-	-	Reserved
`0xEF8`	EDITOCTRL	WO	32-bit	10.8.3 External Debug Integration Output Control Register
`0xEFC`	EDITISR	RO	32-bit	10.8.4 External Debug Integration Input Status Register
`0xF00`	EDITCTRL	RW	32-bit	10.8.5 External Debug Integration Mode Control Register
`0xF04`-`0xF9C`	-	-	-	Reserved
`0xFA0`	DBGCLAIMSET_EL1	RW	32-bit	Debug Claim Tag Set Register ^a
`0xFA4`	DBGCLAIMCLR_EL1	RW	32-bit	Debug Claim Tag Clear Register ^a
`0xFA8`	EDDEVAFF0	RO	32-bit	External Debug Device Affinity Register 0. See 4.3.2 Multiprocessor Affinity Register, EL1
`0xFAC`	EDDEVAFF1	RO	32-bit	External Debug Device Affinity Register 1, RES0
`0xFB0`	EDLAR	WO	32-bit	External Debug Lock Access Register ^a
`0xFB4`	EDLSR	RO	32-bit	External Debug Lock Status Register ^a
`0xFB8`	DBGAUTHSTATUS_EL1	RO	32-bit	Debug Authentication Status Register ^a
`0xFBC`	EDDEVARCH	RO	32-bit	External Debug Device Architecture Register ^a
`0xFC0`	EDDEVID2	RO	32-bit	External Debug Device ID Register 2, RES0
`0xFC4`	EDDEVID1	RO	32-bit	10.8.6 External Debug Device ID Register 1
`0xFC8`	EDDEVID	RO	32-bit	10.8.7 External Debug Device ID Register 0
`0xFCC`	EDDEVTYPE	RO	32-bit	External Debug Device Type Register ^a
`0xFD0`	EDPIDR4	RO	32-bit	External Debug Peripheral Identification Register 4
`0xFD4`-`0xFDC`	EDPIDR5-7	RO	32-bit	External Debug Peripheral Identification Register 5-7
`0xFE0`	EDPIDR0	RO	32-bit	External Debug Peripheral Identification Register 0
`0xFE4`	EDPIDR1	RO	32-bit	External Debug Peripheral Identification Register 1
`0xFE8`	EDPIDR2	RO	32-bit	External Debug Peripheral Identification Register 2
`0xFEC`	EDPIDR3	RO	32-bit	External Debug Peripheral Identification Register 3
`0xFF0`	EDCIDR0	RO	32-bit	External Debug Component Identification Register 0
`0xFF4`	EDCIDR1	RO	32-bit	External Debug Component Identification Register 1
`0xFF8`	EDCIDR2	RO	32-bit	External Debug Component Identification Register 2
`0xFFC`	EDCIDR3	RO	32-bit	External Debug Component Identification Register 3

See the ARM^® Architecture Reference Manual ARMv8 for more information.

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