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Home > Debug > Memory-mapped register summary |
The following table shows the offset address for the registers that are accessible from the internal memory-mapped interface or the external debug interface.
Table 10-10 Memory-mapped debug register summary
Offset | Name | Type | Width | Description |
---|---|---|---|---|
-
|
- | - | - | Reserved |
|
EDESR | RW | 32-bit | External Debug Event Status Register |
|
EDECR | RW | 32-bit | External Debug Execution Control Register a |
-
|
- | - | - | Reserved |
|
EDWARlo | RO | 32-bit | External Debug Watchpoint Address Register, low word a |
|
EDWARhi | RO | 32-bit | External Debug Watchpoint Address Register, high word a |
-
|
- | - | - | Reserved |
|
DBGDTRRX_EL0 | RW | 32-bit | Debug Data Transfer Register, Receive a |
|
EDITR | WO | 32-bit | External Debug Instruction Transfer Register a |
|
EDSCR | RW | 32-bit |
External Debug Status and Control Register a
|
|
DBGDTRTX_EL0 | RW | 32-bit | Debug Data Transfer Register, Transmit a |
|
EDRCR | WO | 32-bit | External Debug Reserve Control Register a |
|
EDACR | RW | 32-bit | 10.8.2 External Debug Auxiliary Control Register. |
|
EDECCR | RW | 32-bit | External Debug Exception Catch Control Register a |
|
- | - | - | Reserved |
|
EDPCSRlo | RO | 32-bit | External Debug Program Counter Sample Register, low word a |
|
EDCIDSR | RO | 32-bit | External Debug Context ID Sample Register a |
|
EDVIDSR | RO | 32-bit | External Debug Virtual Context Sample Register a |
|
EDPCSRhi | RO | 32-bit | External Debug Program Counter Sample Register, high word a |
-
|
- | - | - | Reserved |
|
OSLAR_EL1 | WO | 32-bit | Debug OS Lock Access Register a |
-
|
- | - | - | Reserved |
|
EDPRCR | RW | 32-bit | External Debug Power/Reset Control Register a |
|
EDPRSR | RO | 32-bit | External Debug Processor Status Register a |
-
|
- | - | - | Reserved |
|
DBGBVR0_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 0 a |
|
DBGBVR0_EL1[63:32] | |||
|
DBGBCR0_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGBVR1_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 1 a |
|
DBGBVR1_EL1[63:32] | |||
|
DBGBCR1_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGBVR2_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 2 a |
|
DBGBVR2_EL1[63:32] | |||
|
DBGBCR2_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGBVR3_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 3 a |
|
DBGBVR3_EL1[63:32] | |||
|
DBGBCR3_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGBVR4_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 4 a |
|
DBGBVR4_EL1[63:32] | |||
|
DBGBCR4_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGBVR5_EL1[31:0] | RW | 32-bit | Debug Breakpoint Value Register 5 a |
|
DBGBVR5_EL1[63:32] | |||
|
DBGBCR5_EL1 | RW | 32-bit | 10.4.1 Debug Breakpoint Control Registers, EL1 |
-
|
- | - | - | Reserved |
|
DBGWVR0_EL1[31:0] | RW | 32-bit | Debug Watchpoint Value Register 0 a |
|
DBGWVR0_EL1[63:32] | |||
|
DBGWCR0_EL1 | RW | 32-bit | 10.4.2 Debug Watchpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGWVR1_EL1[31:0] | RW | 32-bit | Debug Watchpoint Value Register 1 a |
|
DBGWVR1_EL1[63:32] | |||
|
DBGWCR1_EL1 | RW | 32-bit | 10.4.2 Debug Watchpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGWVR2_EL1[31:0] | RW | 32-bit | Debug Watchpoint Value Register 2 a |
|
DBGWVR2_EL1[63:32] | |||
|
DBGWCR2_EL1 | RW | 32-bit | 10.4.2 Debug Watchpoint Control Registers, EL1 |
|
- | - | - | Reserved |
|
DBGWVR3_EL1[31:0] | RW | 32-bit | Debug Watchpoint Value Register 3 a |
|
DBGWVR3_EL1[63:32] | |||
|
DBGWCR3_EL1 | RW | 32-bit | 10.4.2 Debug Watchpoint Control Registers, EL1 |
-
|
- | - | - | Reserved |
|
MIDR_EL1 | RO | 32-bit | 4.3.1 Main ID Register, EL1 |
-
|
- | - | - | Reserved |
|
ID_AA64PFR0_EL1[31:0] | RO | 32-bit | 4.3.18 AArch64 Processor Feature Register 0, EL1 |
|
ID_AA64PFR0_EL1[63:32] | RO | 32-bit | |
|
ID_AA64DFR0_EL1[31:0] | RO | 32-bit | 4.3.19 AArch64 Debug Feature Register 0, EL1 |
|
ID_AA64DFR0_EL1[63:32] | RO | 32-bit | |
|
ID_AA64ISAR0_EL1[31:0] | RO | 32-bit | 4.3.20 AArch64 Instruction Set Attribute Register 0, EL1 |
|
ID_AA64ISAR0_EL1[63:32] | RO | 32-bit | |
|
ID_AA64MMFR0_EL1[31:0] | RO | 32-bit | 4.3.21 AArch64 Memory Model Feature Register 0, EL1 |
|
ID_AA64MMFR0_EL1[63:32] | RO | 32-bit | |
|
ID_AA64PFR1_EL1[31:0] | RO | 32-bit | AArch64 Processor Feature Register 1 low word, RES0 |
|
ID_AA64PFR1_EL1[63:32] | RO | 32-bit | AArch64 Processor Feature Register 1 high word, RES0 |
|
ID_AA64DFR1_EL1[31:0] | RO | 32-bit | AArch64 Debug Feature Register 1 low word, RES0 |
|
ID_AA64DFR1_EL1[63:32] | RO | 32-bit | AArch64 Debug Feature Register 1 high word, RES0 |
|
ID_AA64ISAR1_EL1[31:0] | RO | 32-bit | AArch64 Instruction Set Attribute Register 1 low word, RES0 |
|
ID_AA64ISAR1_EL1[63:32] | RO | 32-bit | AArch64 Instruction Set Attribute Register 1 high word, RES0 |
|
ID_AA64MMFR1_EL1[31:0] | RO | 32-bit | AArch64 Memory Model Feature Register 1 low word, RES0 |
|
ID_AA64MMFR1_EL1[63:32] | RO | 32-bit | AArch64 Memory Model Feature Register 1 high word, RES0 |
-
|
- | - | - | Reserved |
|
EDITOCTRL | WO | 32-bit | 10.8.3 External Debug Integration Output Control Register |
|
EDITISR | RO | 32-bit | 10.8.4 External Debug Integration Input Status Register |
|
EDITCTRL | RW | 32-bit | 10.8.5 External Debug Integration Mode Control Register |
-
|
- | - | - | Reserved |
|
DBGCLAIMSET_EL1 | RW | 32-bit | Debug Claim Tag Set Register a |
|
DBGCLAIMCLR_EL1 | RW | 32-bit | Debug Claim Tag Clear Register a |
|
EDDEVAFF0 | RO | 32-bit | External Debug Device Affinity Register 0. See 4.3.2 Multiprocessor Affinity Register, EL1 |
|
EDDEVAFF1 | RO | 32-bit | External Debug Device Affinity Register 1, RES0 |
|
EDLAR | WO | 32-bit | External Debug Lock Access Register a |
|
EDLSR | RO | 32-bit | External Debug Lock Status Register a |
|
DBGAUTHSTATUS_EL1 | RO | 32-bit | Debug Authentication Status Register a |
|
EDDEVARCH | RO | 32-bit | External Debug Device Architecture Register a |
|
EDDEVID2 | RO | 32-bit | External Debug Device ID Register 2, RES0 |
|
EDDEVID1 | RO | 32-bit | 10.8.6 External Debug Device ID Register 1 |
|
EDDEVID | RO | 32-bit | 10.8.7 External Debug Device ID Register 0 |
|
EDDEVTYPE | RO | 32-bit | External Debug Device Type Register a |
|
EDPIDR4 | RO | 32-bit | External Debug Peripheral Identification Register 4 |
-
|
EDPIDR5-7 | RO | 32-bit | External Debug Peripheral Identification Register 5-7 |
|
EDPIDR0 | RO | 32-bit | External Debug Peripheral Identification Register 0 |
|
EDPIDR1 | RO | 32-bit | External Debug Peripheral Identification Register 1 |
|
EDPIDR2 | RO | 32-bit | External Debug Peripheral Identification Register 2 |
|
EDPIDR3 | RO | 32-bit | External Debug Peripheral Identification Register 3 |
|
EDCIDR0 | RO | 32-bit | External Debug Component Identification Register 0 |
|
EDCIDR1 | RO | 32-bit | External Debug Component Identification Register 1 |
|
EDCIDR2 | RO | 32-bit | External Debug Component Identification Register 2 |
|
EDCIDR3 | RO | 32-bit | External Debug Component Identification Register 3 |