10.8.2 External Debug Auxiliary Control Register

The EDACR characteristics are:
Purpose
Provides IMPLEMENTATION DEFINED configuration and control options.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - RO RW
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDACR is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDACR bit assignments.
Figure 10-8 EDACR bit assignments
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The following table shows the EDACR bit assignments.

Table 10-12 EDACR bit assignments

Bits Name Function
[31:4] -
Reserved, RES0.
[3] Override idle Acknowledgment
Override idle Acknowledgment signal to processor. The possible values are:
0Processor waits for the debug register access logic to go idle before it enters the idle state. This is the reset value.
1Processor does not wait for the debug register access logic to go idle before it enters the idle state.
[2] Core debug reset status
Read-only status bit that reflects the current reset state of the debug logic in the processor power domain:
0Debug logic in processor power domain is not in reset state.
1Debug logic in processor power domain is currently in reset state.
[1] Debug powerdown override
Debug powerdown control bit. If debug is enabled and this bit is:
0Error response is generated for APB accesses to the processor domain debug registers when the processor is powered down or OS Double Lock is set. This is the reset value.
1APB accesses to the processor domain debug registers proceed normally when the processor is powered down or OS Double Lock is set.
[0] Debug clock stop control
Debug clock control bit. If debug is enabled and this bit is:
0Does not prevent the clock generator from stopping the processor clock. This is the reset value.
1Prevents the clock generator from stopping the processor clock.
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