10.8.5 External Debug Integration Mode Control Register

The EDITCTRL characteristics are:
Enables the external debug to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the processor, for integration testing or topology detection.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Error Error Error - RO RW
Table 11-1 External register access conditions describes the access conditions.
EDITCTRL is in the Core power domain.
See 10.7 Memory-mapped register summary.
The following figure shows the EDITCTRL bit assignments.
Figure 10-11 EDITCTRL bit assignments
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The following table shows the EDITCTRL bit assignments.

Table 10-15 EDITCTRL bit assignments

Bits Name Function
[31:1] - Reserved, RES0.
[0] IME
When IME is set to 1, the device reverts to an integration mode to enable integration testing or topology detection:
0Normal operation.
1Integration mode enabled.
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