11.3 AArch64 PMU register summary

The PMU counters and their associated control registers are accessible in AArch64 state with MRS and MSR instructions.

The following table shows the PMU registers in AArch64 state. It also shows the offset address for the registers that are accessible from the internal memory-mapped interface or the external debug interface.

Table 11-3 PMU register summary in AArch64 state

Offset Name Type Width Description
0xE04 PMCR_EL0 RW 32-bit 11.4.1 Performance Monitors Control Register, EL0
0xC00 PMCNTENSET_EL0 RW 32-bit Performance Monitors Count Enable Set Register 
0xC20 PMCNTENCLR_EL0 RW 32-bit Performance Monitors Count Enable Clear Register a
0xC80 PMOVSCLR_EL0 RW 32-bit Performance Monitors Overflow Flag Status Register a
0xCA0 PMSWINC_EL0 WO 32-bit Performance Monitors Software Increment Register a
- PMSELR_EL0 RW 32-bit Performance Monitors Event Counter Selection Register a
0xE20 PMCEID0_EL0 RO 32-bit 11.4.2 Performance Monitors Common Event Identification Register 0, EL0
0xE24 PMCEID1_EL0 RO 32-bit Performance Monitors Common Event ID Register 1 a
- PMCCNTR_EL0 RW 64-bit Performance Monitors Cycle Count Register a
- PMXEVTYPER_EL0 RW 32-bit Performance Monitors Selected Event Type Register a
0x47C PMCCFILTR_EL0 RW 32-bit Performance Monitors Cycle Count Filter Register ab
- PMXEVCNTR0_EL0 RW 32-bit Performance Monitors Selected Event Count Register a
- PMUSERENR_EL0 RW 32-bit Performance Monitors User Enable Register a
0xC40 PMINTENSET_EL1 RW 32-bit Performance Monitors Interrupt Enable Set Register a
0xC60 PMINTENCLR_EL1 RW 32-bit Performance Monitors Interrupt Enable Clear Register a
0xCC0 PMOVSSET_EL0 RW 32-bit Performance Monitors Overflow Flag Status Set Register a
0x000 PMEVCNTR0_EL0 RW 32-bit Performance Monitors Event Count Registers a
0x008 PMEVCNTR1_EL0
0x010 PMEVCNTR2_EL0
0x018 PMEVCNTR3_EL0
0x020 PMEVCNTR4_EL0
0x028 PMEVCNTR5_EL0
0x400 PMEVTYPER0_EL0 RW 32-bit Performance Monitors Event Type Registers a
0x404 PMEVTYPER1_EL0
0x408 PMEVTYPER2_EL0
0x40C PMEVTYPER3_EL0
0x410 PMEVTYPER4_EL0
0x414 PMEVTYPER5_EL0
0x47C PMCCFILTR_EL0 RW 32-bit Performance Monitors Cycle Count Filter Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b
The CP15 encoding provides access to PMCCFILTR_EL0 only when PMSELR_EL0.SEL==31.
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