11.4.1 Performance Monitors Control Register, EL0

The PMCR_EL0 characteristics are:

PurposeProvides information on the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
Usage constraints
The accessibility of the PMCR_EL0 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
Config RW RW RW RW RW
The external accessibility to the PMCR_EL0 by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error Error Error RO/WI RW
Table 11-1 External register access conditions describes the access conditions.
Configurations
The PMCR_EL0 is Common to Secure and Non-secure states and architecturally mapped to:
  • The AArch32 PMCR register.
  • The external PMCR_EL0 register.
Attributes
The following figure shows the PMCR_EL0 bit assignments for a System register access.
Figure 11-2 PMCR_EL0 bit assignments
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The following table shows the PMCR_EL0 bit assignments for a System register access.

Table 11-4 PMCR_EL0 bit assignments

Bits Name Function
[31:24] IMP
Implementer code:
0x41ARM.
This is a read-only field.
[23:16] IDCODE
Identification code:
0x02Cortex-A72 processor.
This is a read-only field.
[15:11] N
Number of event counters.
In Non-secure modes other than Hyp mode, this field reads the value of HDCR.HPMN. See 4.5.12 Hyp Debug Control Register.
In Secure state and Hyp mode, this field returns 0x6 that indicates the number of counters implemented.
This is a read-only field.
[10:7] - Reserved, RES0.
[6] LC
Long cycle count enable. Selects which PMCCNTR_EL0 bit generates an overflow recorded in PMOVSR[31]:
0Overflow on increment that changes PMCCNTR_EL0[31] from 1 to 0.
1Overflow on increment that changes PMCCNTR_EL0[63] from 1 to 0.
[5] DP
Disable cycle counter, PMCCNTR_EL0 when event counting is prohibited:
0Cycle counter operates regardless of the non-invasive debug authentication settings.
1Cycle counter is disabled if non-invasive debug is not permitted and enabled.
This bit is read/write.
[4] X
Export enable. This bit permits events to be exported to another debug device, such as a trace macrocell, over an event bus:
0Export of events is disabled.
1Export of events is enabled.
This bit is read/write and does not affect the generation of Performance Monitors interrupts, that can be implemented as a signal exported from the processor to an interrupt controller.
[3] D
Clock divider:
0When enabled, PMCCNTR_EL0 counts every clock cycle.
1When enabled, PMCCNTR_EL0 counts every 64 clock cycles.
This bit is read/write.
[2] C
Clock counter reset:
0No action.
1Reset PMCCNTR_EL0 to 0.

Note

Resetting PMCCNTR does not clear the PMCCNTR_EL0 overflow bit to 0. See the ARM® Architecture Reference Manual ARMv8 for more information.
This bit is write-only, and always RAZ.
[1] P
Event counter reset:
0No action.
1Reset all event counters, not including PMCCNTR_EL0, to 0.
In Non-secure modes other than Hyp mode, a write of 1 to this bit does not reset event counters that the HDCR.HPMN field reserves for Hyp mode use. See 4.5.12 Hyp Debug Control Register.
In Secure state and Hyp mode, a write of 1 to this bit resets all the event counters.
[0] E
Enable bit. This bit does not disable or enable, counting by event counters reserved for Hyp mode by HDCR.HPMN. It also does not suppress the generation of performance monitor overflow interrupt requests by those counters:
0All counters, including PMCCNTR_EL0, are disabled. This is the reset value.
1All counters are enabled.
This bit is read/write.
To access the PMCR_EL0 in AArch64 state, read or write the register with:
MRS <Xt>, PMCR_EL0; Read Performance Monitors Control Register
MSR PMCR_EL0, <Xt>; Write Performance Monitors Control Register
To access the PMCR in AArch32 state, read or write the CP15 registers with:
MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitors Control Register
MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitors Control Register
See 11.7.1 Performance Monitors Control Register, EL0 for information about accessing the PMCR_EL0 through the internal memory-mapped interface and the external debug interface.
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