11.7.7 Performance Monitors Cycle Counter Snapshot Register

The PMCCNTSR characteristics are:
Purpose
Captures a copy of the PMCCNTR_EL0 register. After capture, writes to PMCCNTR_EL0 and PMCR_EL0.C do not affect the PMCCNTSR value.
Usage constraints
The external accessibility to the PMCCNTSR by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error RO RO RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
There is no configuration information for PMCCNTSR.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information about the PMCCNTR_EL0 register.
PMCCNTSR[31:0] can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x618.
PMCCNTSR[63:32] can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x61C.
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