11.7.8 Performance Monitors Event Counters Snapshot Registers

The PMEVCNTSRn characteristics are:
Purpose
Captures a copies of the PMEVCNTRn_EL0 registers. After capture, writes to PMEVCNTRn_EL0 and PMCR_EL0.P do not affect the PMEVCNTSRn value.

Note

The range of n for PMEVCNTSRn is 0 to 5.
Usage constraints
The external accessibility to the PMEVCNTSRn by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error RO RO RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
There is no configuration information for PMEVCNTSRn.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information about the PMEVCNTRn_EL0 registers.
The PMEVCNTRn_EL0 registers can be accessed through the internal memory-mapped interface and the external debug interface, offsets 0x620-0x634.
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