11.7.10 Performance Monitors Snapshot Reset Register

The PMSRR characteristics are:
PurposeReset the cycle counter and the performance counters.
Usage constraints
The external accessibility to the PMSRR by condition code is:
Off DLK OSLK EPMAD SLK Default
Error Error RW RW RW RW
Table 11-1 External register access conditions describes the condition codes.
ConfigurationsThere is no configuration information for PMSRR.
AttributesSee the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMSRR bit assignments.
Figure 11-7 PMSRR bit assignments
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The following table shows the PMSRR bit assignments.

Table 11-11 PMSRR bit assignments

Bits Name Function
[31] RC
Reset cycle counter. Indicates whether the PMCCNTR_EL0 and PMOVSR[31] are reset after a capture:
0PMCCNTR_EL0 and PMOVSR[31] are not reset on capture.
1PMCCNTR_EL0 and PMOVSR[31] are reset on capture.
[30:6] - Reserved, RES0.
[5] RP5
Reset performance counter 5. Indicates whether PMEVCNTR5_EL0 and PMOVSR[5] are reset after a capture:
0PMEVCNTR5_EL0 and PMOVSR[5] are not reset on capture.
1PMEVCNTR5_EL0 and PMOVSR[5] are reset on capture.
[4] RP4
Reset performance counter 4. Indicates whether PMEVCNTR4_EL0 and PMOVSR[4] are reset after a capture:
0PMEVCNTR4_EL0 and PMOVSR[4] are not reset on capture.
1PMEVCNTR4_EL0 and PMOVSR[4] are reset on capture.
[3] RP3
Reset performance counter 3. Indicates whether PMEVCNTR3_EL0 and PMOVSR[3] are reset after a capture:
0PMEVCNTR3_EL0 and PMOVSR[3] are not reset on capture.
1PMEVCNTR3_EL0 and PMOVSR[3] are reset on capture.
[2] RP2
Reset performance counter 2. Indicates whether PMEVCNTR2_EL0 and PMOVSR[2] are reset after a capture:
0PMEVCNTR2_EL0 and PMOVSR[2] are not reset on capture.
1PMEVCNTR2_EL0 and PMOVSR[2] are reset on capture.
[1] RP1
Reset performance counter 1. Indicates whether PMEVCNTR1_EL0 and PMOVSR[1] are reset after a capture:
0PMEVCNTR1_EL0 and PMOVSR[1] are not reset on capture.
1PMEVCNTR1_EL0 and PMOVSR[1] are reset on capture.
[0] RP0
Reset performance counter 0. Indicates whether PMEVCNTR0_EL0 and PMOVSR[0] are reset after a capture:
0PMEVCNTR0_EL0 and PMOVSR[0] are not reset on capture.
1PMEVCNTR0_EL0 and PMOVSR[0] are reset on capture.
The PMSRR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x6F4.
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