11.7.11 Performance Monitors Configuration Register

The PMCFGR characteristics are:
Contains PMU specific configuration data.
Usage constraints
The accessibility to the PMCFGR by condition code is:
Error Error Error Error RO RO
Table 11-1 External register access conditions describes the condition codes.
The PMCFGR is in the Core power domain.
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCFGR bit assignments.
Figure 11-8 PMCFGR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMCFGR bit assignments.

Table 11-12 PMCFGR bit assignments

Bits Name Function
[31:17] -
Reserved, RES0.
[16] EX
Export supported. The value is:
1Export is supported. PMCR_EL0.EX is read/write.
[15] CCD
Cycle counter has pre-scale. The value is:
1PMCR_EL0.D is read/write.
[14] CC
Dedicated cycle counter supported. The value is:
1Dedicated cycle counter is supported.
[13:8] Size
Counter size. The value is:
0b11111164-bit counters.
[7:0] N
Number of event counters. The value is:
0x06Six counters.
The PMCFGR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE00.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.