12.5.1 External register access permissions

External access permission to the cross trigger registers is subject to the conditions at the time of the access. The following table describe the processor response to accesses through the external debug and memory-mapped interfaces.

Table 12-4 External register access conditions

Condition code Condition Description
Off EDPRSR.PU is 0
Core power domain is completely off, or in a low-power state where the core power domain registers cannot be accessed.

Note

If debug is powered down, all external debug and memory-mapped register accesses return an error.
DLK EDPRSR.DLK is 1 OS Double Lock is locked.
OSLK OSLSR_EL1.OSLK is 1 OS Lock is locked.
EDAD AllowExternalDebugAccess() ==FALSE External debug access disabled. When an error is returned because of the EDAD condition code, and this is the highest priority error condition, EDPRSR.SDAD is set to 1. Otherwise EDPRSR.SDAD is unchanged.
SLK Memory-mapped interface only Software Lock is locked. For the external debug interface, ignore this code.
Default - None of the conditions apply, normal access.
The following table shows an example of external register access conditions for access to a cross trigger register. To determine the access permission for the register, scan the columns from left to right. Stop at the first column whose condition is true, the entry gives the access permission of the register and scanning stops.

Table 12-5 External register access conditions example

Off DLK OSLK EDAD SLK Default
- - - - RO/WI RO
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