This section describes the implementation-specific ETM registers in the Cortex-A72 processor.
13.7.1 Trace Configuration Register.
13.7.2 Trace Auxiliary Control Register.
13.7.3 Trace Event Control 0 Register.
13.7.4 Trace Event Control 1 Register.
13.7.5 Trace Synchronization Period Register.
13.7.6 Trace Cycle Count Control Register.
13.7.7 Trace ID Register.
13.7.8 ViewInst Main Control Register.
13.7.9 External Input Select Register.
13.7.10 ID Register 8.
13.7.11 ID Register 9.
13.7.12 ID Register 10.
13.7.13 ID Register 11.
13.7.14 ID Register 12.
13.7.15 ID Register 13.
13.7.16 Implementation Defined Register 0.
13.7.17 Trace ID Register 0.
13.7.18 Trace ID Register 1.
13.7.19 Trace ID Register 2.
13.7.20 Trace ID Register 3.
13.7.21 Trace ID Register 4.
13.7.22 Trace ID Register 5.
13.7.23 Resource Selection Control Registers.
13.7.24 Address Comparator Access Type Registers.
13.7.25 Context ID Comparator Value Register 0.
13.7.26 VMID Comparator Value Register 0.
13.7.27 Context ID Comparator Control Register 0.
13.7.28 Trace Integration Miscellaneous Outputs Register.
13.7.29 Trace Integration Miscellaneous Input Register.
13.7.30 Trace Integration Test ATB Data Register 0.
13.7.31 Trace Integration Test ATB Control Register 2.
13.7.32 Trace Integration Test ATB Control Register 1.
13.7.33 Trace Integration Test ATB Control Register 0.
13.7.34 Trace Integration Mode Control register.
13.7.35 Trace Device Affinity register 0.
13.7.36 Trace Device Affinity register 1.
13.7.37 Trace Peripheral Identification Registers.
13.7.38 Trace Component Identification Registers.