13.7.3 Trace Event Control 0 Register

The TRCEVENTCTL0R characteristics are:
Purpose
Controls the tracing of arbitrary events. Each of the event fields in this register is an event selector.
If any of the selected events occur and the corresponding bit in TRCEVENTCTL1R.INSTEN is 1, then an event element is generated in the instruction trace stream.
If any of the selected events occur and the corresponding bit in TRCEVENTCTL1R.DATAEN is 1, then an event element is generated in the data trace stream.
Usage constraints
Only accepts writes when the trace unit is disabled.
Configurations
Available in all configurations.
Attributes
A 32-bit RW trace register.
The following figure shows the TRCEVENTCTL0R bit assignments.
Figure 13-4 TRCEVENTCL0R bit assignments
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The following table shows the TRCEVENTCTL0R bit assignments.

Table 13-6 TRCEVENTCL0R bit assignments

Bits Name Function
[31:24] Event3 Identifies the fourth event to trace
[23:16] Event2 Identifies the third event to trace
[15:8] Event1 Identifies the second event to trace
[7:0] Event0 Identifies the first event to trace
The TRCEVENTCTL0R can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x020.
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