13.7.5 Trace Synchronization Period Register

The TRCSYNCPR characteristics are:
Controls how often periodic trace synchronization requests occur.
Usage constraints
Only accepts writes when the trace unit is disabled.
This register must be programmed.
Available in all configurations.
A 32-bit RW trace register.
The following figure shows the TRCSYNCPR bit assignments.
Figure 13-6 TRCSYNCPR bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the TRCSYNCPR bit assignments.

Table 13-8 TRCSYNCPR bit assignments

Bits Name Function
[31:5] - Reserved, RES0.
[4:0] Period
Controls how many bytes of trace, the sum of instruction and data, that a trace unit can generate before a periodic trace synchronization request occurs.
When 0b00000, periodic trace synchronization requests are disabled. This setting does not disable other types of trace synchronization request.
The number of bytes is always a power of two and the permitted values are:
0b01000Periodic trace synchronization request occurs after 28, or 256 bytes of trace.
0b01001Periodic trace synchronization request occurs after 29, or 512 bytes of trace.
0b01010Periodic trace synchronization request occurs after 210, or 1024 bytes of trace.
0b10100Periodic trace synchronization request occurs after 220, or 1048576 bytes of trace.
The TRCSYNCPR can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x034.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.