13.7.16 Implementation Defined Register 0

The TRCIMSPEC0 characteristics are:
TRCIMSPEC0 is partially implemented for the future implementation of up to eight IMPLEMENTATION DEFINED registers so that a debugger can implement a general mechanism for detecting the IMPLEMENTATION DEFINED registers. This register must be implemented.
Usage constraints
There are no usage constraints.
Available in all configurations.
A 32-bit RW trace register. This register is reset by a trace unit reset.
The following figure shows the TRCIMSPEC0 bit assignments.
Figure 13-17 TRCIMSPEC0 bit assignments
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The following table shows the TRCIMSPEC0 bit assignments.

Table 13-19 TRCIMSPEC0 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0.
[7:4] EN EN is RES0 when the SUPPORT field is 0b0000.
Indicates whether the implementation supports IMPLEMENTATION DEFINED features. This value is:
0b0000No IMPLEMENTATION DEFINED features are supported.
The TRCIMSPEC0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1C0.
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