13.7.17 Trace ID Register 0

The TRCIDR0 characteristics are:
Returns the tracing capabilities of the trace unit.
Usage constraints
There are no usage constraints.
Available in all configurations.
See 13.6 Register summary.
The following figure shows the TRCIDR0 bit assignments.
Figure 13-18 TRCIDR0 bit assignments
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The following table shows the TRCIDR0 bit assignments.

Table 13-20 TRCIDR0 bit assignments

Bits Name Function
[31:30] - Reserved, RES0.
Commit mode field. This value is:
1Commit mode 1.
[28:24] TSSIZE
Global timestamp size field. This value is:
0b01000Implementation supports a maximum global timestamp of 64 bits.
[23:17] - Reserved, RES0.
[16:15] QSUPP
Q element support field. This value is:
0b00Q element support is not implemented. TRCCONFIGR is RES0.
[14] QFILT QFILT is RES0 when QSUPP is 0b00.
[13:12] CONDTYPE CONDTYPE is RES0 when TRCCOND is 0b0.
[11:10] NUMEVENT
Number of events field. Indicates how many events the trace unit supports. This value is:
0b11The trace unit supports 4 events.
Return stack bit. Indicates whether the implementation supports a return stack. This value is:
1Return stack is implemented. TRCCONFIGR.RS is supported.
[8] - Reserved, RES0.
Cycle counting instruction bit. Indicates whether the trace unit supports cycle counting for instructions. This value is:
Cycle counting in the instruction trace is implemented, therefore:
  • TRCCONFIGR.CCI is supported.
  • TRCCCTLR is supported.
Conditional instruction tracing support bit. Indicates whether the trace unit supports conditional instruction tracing. This value is:
0Conditional instruction tracing is not supported.
Branch broadcast tracing support bit. Indicates whether the trace unit supports branch broadcast tracing. This value is:
Branch broadcast tracing is supported, therefore:
  • TRCCONFIGR.CCI is supported.
  • TRCBBCTLR is supported.
Conditional tracing field. This value is:
Data tracing is not supported.
[2:1] INSTP0
P0 tracing support field. This value is:
0b00Tracing of load and store instructions as P0 elements is not supported.
[0] - Reserved, RES1.
The TRCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1E0.
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