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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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13.7.18 Trace ID Register 1

The TRCIDR1 characteristics are:
Purpose
Returns the base architecture of the trace unit.
Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes
See 13.6 Register summary.
The following figure shows the TRCIDR1 bit assignments.
Figure 13-19 TRCIDR1 bit assignments
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The following table shows the TRCIDR1 bit assignments.

Table 13-21 TRCIDR1 bit assignments

Bits Name Function
[31:24] Designer
Indicates which company designed the trace unit. The value is:
0x41ARM
[23:16] - Reserved, RES0.
[15:12] - Reserved, RES1.
[11:8] TRCARCHMAJ
Indicates the major version number of the trace unit architecture. The value is:
0x4Indicates ETMv4.
All other values are reserved.
[7:4] TRCARCHMIN
Identifies the minor version number of the trace unit architecture. The value is:
0x0Identifies the minor version number of the trace unit architecture.
[3:0]
Revision
Identifies the revision of:
  • The trace registers.
  • The OS Lock registers.
0Revision value.
The TRCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0x1E4.
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