The TRCDEVAFF0 characteristics are:
- The value is a read-only copy of MPIDR_EL1[31:0]
as seen from EL3, unaffected by VMPIDR_EL2.
- Usage constraints
- Accessible only from the memory-mapped interface
or from an external agent such as a debugger.
- Available in all configurations.
A 32-bit RO management register.
For the Cortex-A72
MPIDR_EL1[31:0] is architecturally mapped to the AArch32 register MPIDR.
The TRCDEVAFF0 can be accessed through the internal memory-mapped
interface and the external debug interface, offset