13.7.36 Trace Device Affinity register 1

The TRCDEVAFF1 characteristics are:
The value is a read-only copy of MPIDR_EL1[63:32] as seen from EL3, unaffected by VMPIDR_EL2.
Usage constraints
Accessible only from the memory-mapped interface or from an external agent such as a debugger.
Available in all configurations.
A 32-bit RO management register.
For the Cortex-A72 processor, MPIDR_EL1[63:32] is RES0.
The TRCDEVAFF1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFAC.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.