14.3 AArch64 register summary

The following table gives a summary of the Cortex-A72 processor Advanced SIMD and Floating-point System registers in AArch64 state. All AArch64 registers are 32-bit wide.

Table 14-2 AArch64 Advanced SIMD and Floating-point System registers

Name Type Reset Description
FPCR RW 0x00000000 See 14.4.1 Floating-point Control Register
FPSR RW 0x00000000 See 14.4.2 Floating-point Status Register
MVFR0_EL1 RO 0x10110222 See 14.4.3 Media and VFP Feature Register 0, EL1
MVFR1_EL1 RO 0x12111111 See 14.4.4 Media and VFP Feature Register 1, EL1
MVFR2_EL1 RW 0x00000043 See 14.4.5 Media and VFP Feature Register 2, EL1
FPEXC32_EL2 RW 0x00000700 See 14.4.6 Floating-point Exception Control Register 32, EL2
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