Non-Confidential | ![]() | ARM 100095_0002_03_en | ||
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Home > Advanced SIMD and Floating-point > AArch64 register descriptions > Floating-point Control Register |
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
RW | RW | RW | RW | RW | RW |
Table 14-3 FPCR bit assignments
Bits
|
Name
|
Function | ||||||||
---|---|---|---|---|---|---|---|---|---|---|
[31:27]
|
- | Reserved, RES0. | ||||||||
[26]
|
AHP | Alternative half-precision
control bit:
|
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[25] | DN | Default NaN mode control
bit:
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[24] | FZ | Flush-to-zero mode control
bit:
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[23:22] | RMode | Rounding Mode control field:
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[21:0] | - | Reserved, RES0. |
MRS <Xt>, FPCR; Read Floating-point Control Register MSR FPCR, <Xt>; Write Floating-point Control Register