14.4.1 Floating-point Control Register

The FPCR characteristics are:
Controls floating-point extension behavior.
Usage constraints
The accessibility to the FPCR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The FPCR is part of the Floating-point functional group.
The named fields in this register map to the equivalent fields in the AArch32 FPSCR.
See the register summary in Table 14-2 AArch64 Advanced SIMD and Floating-point System registers.
The following figure shows the FPCR bit assignments.
Figure 14-1 FPCR bit assignments
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The following table shows the FPCR bit assignments.

Table 14-3 FPCR bit assignments

- Reserved, RES0.
Alternative half-precision control bit:
0IEEE half-precision format selected.
1Alternative half-precision format selected.
[25] DN
Default NaN mode control bit:
0NaN operands propagate through to the output of a floating-point operation.
1Any operation involving one or more NaNs returns the Default NaN.
[24] FZ
Flush-to-zero mode control bit:
0Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
1Flush-to-zero mode enabled.
[23:22] RMode
Rounding Mode control field:
0b00Round to Nearest (RN) mode.
0b01Round towards Plus Infinity (RP) mode.
0b10Round towards Minus Infinity (RM) mode.
0b11Round towards Zero (RZ) mode.
[21:0] - Reserved, RES0.
To access FPCR in AArch64 state, read or write the register with:
MRS <Xt>, FPCR; Read Floating-point Control Register
MSR FPCR, <Xt>; Write Floating-point Control Register
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