14.4.2 Floating-point Status Register

The FPSR characteristics are:
Purpose
Provides floating-point system status information.
Usage constraints
The accessibility to the FPSR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
RW RW RW RW RW RW
Configurations
The FPSR is part of the Floating-point functional group.
The named fields in this register map to the equivalent fields in the AArch32 FPSCR.
Attributes
See the register summary in Table 14-2 AArch64 Advanced SIMD and Floating-point System registers.
The following figure shows the FPSR bit assignments.
Figure 14-2 FPSR bit assignments
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The following table shows the FPSR bit assignments.

Table 14-4 FPSR bit assignments

Bits
Name
Function
[31]
N
Negative condition flag for floating-point comparison operations:
AArch32Negative condition flag.
AArch64Sets the N bit in the main processor state (PSTATE) condition code flag.
[30]
Z
Zero condition flag for floating-point comparison operations:
AArch32Zero condition flag.
AArch64Sets the PSTATE.Z condition code flag.
[29] C
Carry condition flag for floating-point comparison operations:
AArch32Carry condition flag.
AArch64Sets the PSTATE.C condition code flag.
[28] V
Overflow condition flag for floating-point comparison operations:
AArch32Overflow condition flag.
AArch64Sets the PSTATE.V condition code flag.
[27] QC Cumulative saturation bit, Advanced SIMD only. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since 0 was last written to this bit.
[26:8] - Reserved, RES0.
[7] IDC Input Denormal cumulative exception bit. This bit is set to 1 to indicate that the Input Denormal exception has occurred since 0 was last written to this bit.
[6:5] - Reserved, RES0.
[4] IXC Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit.
[3] UFC Underflow cumulative exception bit. This bit is set to 1 to indicate that the Underflow exception has occurred since 0 was last written to this bit.
[2] OFC Overflow cumulative exception bit. This bit is set to 1 to indicate that the Overflow exception has occurred since 0 was last written to this bit.
[1] DZC Division by Zero cumulative exception bit. This bit is set to 1 to indicate that the Division by Zero exception has occurred since 0 was last written to this bit.
[0] IOC Invalid Operation cumulative exception bit. This bit is set to 1 to indicate that the Invalid Operation exception has occurred since 0 was last written to this bit.
To access FPSR in AArch64 state, read or write the register with:
MRS <Xt>, FPSR; Read Floating-point Status Register
MSR FPSR, <Xt>; Write Floating-point Status Register
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