The MVFR2_EL1 characteristics are:
- Purpose
- The MVFR2_EL1 must be interpreted with the MVFR0_EL1 and the MVFR1_EL1
to describe the features provided by the Advanced SIMD and FP functions.
- Usage constraints
The accessibility to the MVFR2_EL1 in AArch64 state
by Exception level is:
| EL0 |
EL1(NS) |
EL1(S) |
EL2 |
EL3(SCR.NS = 1) |
EL3(SCR.NS = 0) |
| - |
RO |
RO |
RO |
RO |
RO |
The accessibility to the MVFR2 in AArch32 state by Exception level
is:
| EL0 |
EL1(NS) |
EL1(S) |
EL2 |
EL3(SCR.NS = 1) |
EL3(SCR.NS = 0) |
| - |
Config |
RO |
Config |
Config |
RO |
- Configurations
The MVFR2_EL1 is:
- Common to Secure and Non-secure states.
- Architecturally mapped to AArch32 MVFR2 register.
- Attributes
- See the register summary in Table 14-2 AArch64 Advanced SIMD and Floating-point System registers.
The following figure shows the MVFR2_EL1 bit assignments.
Figure 14-5 MVFR2_EL1 bit assignments
The following table shows the MVFR2_EL1 bit assignments.
Table 14-7 MVFR2_EL1 bit assignments
| Bits |
Name |
Function |
| [31:8] |
- |
Reserved, RES0. |
| [7:4] |
FPMisc |
Floating-point miscellaneous
features supported. This value is:
0b0100 | Includes support for the following
features:
- Floating-point selection.
- Floating-point Conversion to Integer with Directed
Rounding modes.
- Floating-point Round to Integral floating-point.
- Floating-point MaxNum and MinNum.
|
|
| [3:0] |
SIMDMisc |
Advanced SIMD miscellaneous
features supported. This value is:
0b011 | Includes support for the following
features:
- Floating-point Conversion to Integer with Directed
Rounding modes.
- Floating-point Round to Integral floating-point.
- Floating-point MaxNum and MinNum.
|
|
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