14.4.6 Floating-point Exception Control Register 32, EL2

The FPEXC32_EL2 characteristics are:
Purpose
Provides access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.
Usage constraints
The accessibility to the FPEXC32_EL2 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
The accessibility to the FPEXC in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- Config RW Config Config RW
Configurations
The FPEXC32_EL2 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to AArch32 FPEXC register.
Attributes
See the register summary in Table 14-2 AArch64 Advanced SIMD and Floating-point System registers.
The following figure shows the FPEXC32_EL2 bit assignments.
Figure 14-6 FPEXC32_EL2 bit assignments
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The following table shows the FPEXC32_EL2 bit assignments.

Table 14-8 FPEXC32_EL2 bit assignments

Bits Name Function
[31] EX Exception bit. The Cortex-A72 processor implementation does not generate asynchronous FP exceptions, so this bit is RES0.
[30] EN bit, VFPdescriptionVFP enable bitdescriptionEN
Enable bit. A global enable for the Advanced SIMD and FP functions:
0The Advanced SIMD and FP functions are disabled.
1The Advanced SIMD and FP functions are enabled and operate normally.
The EN bit is cleared at reset. See the ARM® Architecture Reference Manual ARMv8 for more information.
[29:11] - Reserved, RES0.
[10:8] - Reserved, RES1.
[7:0] - Reserved, RES0.

Note

The Cortex-A72 processor implementation does not support deprecated FP short vector feature. You can use software to emulate the short vector feature, if required.
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