14.5 AArch32 register summary

The following table gives a summary of the Advanced SIMD and Floating-point System registers in the Cortex-A72 processor when in AArch32 state.

Table 14-9 AArch32 Advanced SIMD and Floating-point System registers

Name Type Reset Description
FPSID RO 0x41034080 See 14.6.1 Floating-point System ID Register
FPSCR RW 0x00000000 See 14.6.2 Floating-point Status and Control Register
MVFR0 RO 0x10110222 See 14.4.3 Media and VFP Feature Register 0, EL1
MVFR1 RO 0x12111111 See 14.4.4 Media and VFP Feature Register 1, EL1
MVFR2 RW 0x00000043 See 14.4.5 Media and VFP Feature Register 2, EL1
FPEXC RW 0x00000700 See 14.4.6 Floating-point Exception Control Register 32, EL2


The Floating-point Instruction Registers, FPINST and FPINST2 are not implemented, and any attempt to access them is UNPREDICTABLE.
See the ARM® Architecture Reference Manual ARMv8 for information about permitted accesses to the Advanced SIMD and Floating-point System registers.
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