14.6.1 Floating-point System ID Register

The FPSID characteristics are:
Provides top-level information about the floating-point implementation.
Usage constraints
The accessibility to the FPSID by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- Config RO Config Config RO
The FPSID is Common to Secure and Non-secure states.
See the register summary in Table 14-9 AArch32 Advanced SIMD and Floating-point System registers.
The following figure shows the FPSID bit assignments.
Figure 14-7 FPSID bit assignments
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The following table shows the FPSID bit assignments.

Table 14-10 FPSID bit assignments

Bits Name Function
[31:24] Implementer
Indicates the implementer:
0x41ARM Limited.
[23] SW
Software bit. This bit indicates whether a system provides only software emulation of the floating-point instructions:
0x0The system includes hardware support for floating-point operations.
[22:16] Subarchitecture
Subarchitecture version number:
VFPv3 architecture, or later, with no subarchitecture. The entire floating-point implementation is in hardware, and no software support code is required.
The VFP architecture version is indicated by the MVFR0, MVFR1, and MVFR2 registers.
[15:8] PartNum
Indicates the part number for the floating-point implementation:
[7:4] Variant
Indicates the variant number:
0x8Cortex-A72 processor.
[3:0] Revision
Indicates the revision number for the floating-point implementation:
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