Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
Home > Signal Descriptions > ACP interface signals > Read address channel signals

A.11.5 Read address channel signals

The following table shows the read address channel signals for the ACP interface.

Table A-31 Read address channel signals

Signal Type Description
ARREADYS Output
Read address ready.
ARVALIDS Input
Read address valid.
ARIDS[4:0] Input
Read request ID.
ARADDRS[43:0] Input
Read address.
ARLENS[7:0] Input
Read burst length.
ARCACHES[3:0] Input
Read cache type.
ARUSERS[1:0] Input
Read attributes:
[1]Outer Shareable.
[0]Inner Shareable.
ARPROTS[2:0] Input
Read protection type.

Note

The ACP interface uses the AXI4 defined default values for the following input signals:
0b100ARSIZES[2:0].
0b01ARBURSTS[1:0].
0b0ARLOCKS.
Related information
7.8.2 ACP ARUSER and AWUSER signals
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved. 
Home > Signal Descriptions > ACP interface signals > Read address channel signals