10.8.1 External Debug Reserve Control Register

The EDRCR characteristics are:

PurposeUsed to cancel bus requests and clear sticky bits in the EDSCR.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
ERROR ERROR ERROR - WI WO
Table 10-1 External register access conditions describes the access conditions.
ConfigurationsThe EDRCR is in the Core power domain.
AttributesSee the register summary in Table 10-10 Memory-mapped debug register summary.
The following figure shows the EDRCR bit assignments.
Figure 10-7 EDRCR bit assignments
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The following table shows the EDRCR bit assignments.

Table 10-11 EDRCR bit assignments

Bits Name Function
[31:5] -
Reserved, RES0.
[4] CBRRQ
Reserved.RES0.
[3] CSPA
Clear Sticky Pipeline Advance. This bit is used to clear the EDSCR.PipeAdv bit to 0. The possible values are:
0No action.
1Clear the EDSCR.PipeAdv bit to 0.
[2] CSE
Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The possible values:
0No action.
1Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the processor is in Debug state, the EDSCR.ITO bit, to 0.
[1:0] -
Reserved, RES0.
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