8.2.4 GIC bypass modes

This section describes the two GIC bypass modes. The bypass modes are:

GICCDISABLE bypass mode

When using an external standalone interrupt controller such as the ARM GIC-400 or a proprietary interrupt controller, you must set the GICCDISABLE signal HIGH. This forces the GIC CPU interface to operate in bypass mode as described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
When the GICCDISABLE signal is tied HIGH, the PERIPHBASE[43:18] value can be read in the Configuration Base Address Register, to permit software to read the location of the GIC if it exists in the system external to the Cortex-A72 processor.
When the GICCDISABLE signal is HIGH, you must tie these CPU interface input signals LOW:
  • ICDTVALID.
  • ICDTDATA.
  • ICDTLAST.
  • ICDTDEST.
  • ICCTREADY.
When the GICCDISABLE signal is HIGH, you must leave these CPU interface output signals unconnected:
  • ICCTVALID.
  • ICCTDATA.
  • ICCTLAST.
  • ICCTID.
  • ICDTREADY.
  • nVCPUMNTIRQ[N:0].
If GICCDISABLE is tied HIGH, the nVIRQ and nVFIQ inputs can be:
  • Tied off to HIGH if they are not in use.
  • Driven by an external GIC in the SoC.

Software bypass mode

The GIC CPU interface supports software interrupt bypass mode through interrupt disable bypass bits for both memory-mapped accesses and System register accesses. Unlike the GICCDISABLE bypass mode, the software bypass mode does not fully disable the internal GIC CPU interface.

For more information, see the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
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