10.11.4 ROM table Debug Peripheral Identification Registers

The ROM table Debug Peripheral Identification Registers provide standard information required for all components that conform to the ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2. There is a set of eight registers, listed in register number order in the following table.

Table 10-33 Summary of the ROM table Debug Peripheral Identification Registers

Register Value Offset
ROMPID4 0x04 0xFD0
ROMPID5 0x00 0xFD4
ROMPID6 0x00 0xFD8
ROMPID7 0x00 0xFDC
ROMPID0 0xA4 0xFE0
ROMPID1 0xB4 0xFE4
ROMPID2 0x0B 0xFE8
ROMPID3 0x00 0xFEC
Only bits[7:0] of each ROM table Debug Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight ROM table Debug Peripheral ID Registers define a single 64-bit Peripheral ID.
The ROM table Debug Peripheral ID registers are:

ROM table Debug Peripheral Identification Register 0

The ROMPIDR0 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The ROMPIDR0 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMPIDR0 bit assignments.
Figure 10-25 ROMPIDR0 bit assignments
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The following table shows the ROMPIDR0 bit assignments.

Table 10-34 ROMPIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] Part_0
0xA4Least significant byte of the ROM table part number.

ROM table Debug Peripheral Identification Register 1

The ROMPIDR1 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The ROMPIDR1 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMPIDR1 bit assignments.
Figure 10-26 ROMPIDR1 bit assignments
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The following table shows the ROMPIDR1 bit assignments.

Table 10-35 ROMPIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] DES_0
0xBLeast significant nibble of JEP106 ID code. For ARM Limited.
[3:0] Part_1
0x4Most significant nibble of the ROM table part number.

ROM table Debug Peripheral Identification Register 2

The ROMPIDR2 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The ROMPIDR2 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMPIDR2 bit assignments.
Figure 10-27 ROMPIDR2 bit assignments
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The following table shows the ROMPIDR2 bit assignments.

Table 10-36 ROMPIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Revision
0x0Part major revision.
[3] JEDEC
0b1RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011Designer, most significant bits of JEP106 ID code. For ARM Limited.

ROM table Debug Peripheral Identification Register 3

The ROMPIDR3 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The ROMPIDR3 is in the Debug power domain.
Attributes
See the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMPIDR3 bit assignments.
Figure 10-28 ROMPIDR3 bit assignments
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The following table shows the ROMPIDR3 bit assignments.

Table 10-37 ROMPIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] REVAND
0x0Part minor revision.
[3:0] CMOD
0x0Customer modified.

ROM table Debug Peripheral Identification Register 4

The ROMPIDR4 characteristics are:

PurposeProvides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
ConfigurationsThe ROMPIDR4 is in the Debug power domain.
AttributesSee the register summary in Table 10-30 ROM table registers.
The following figure shows the ROMPIDR4 bit assignments.
Figure 10-29 ROMPIDR4 bit assignments
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The following table shows the ROMPIDR4 bit assignments.

Table 10-38 ROMPIDR4 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Size
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
[3:0] DES_2
0x4Designer, JEP106 continuation code, least significant nibble. For ARM Limited.

ROM table Debug Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0.

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