10.8.8 External Debug Peripheral Identification Registers

The External Debug Peripheral Identification Registers provide standard information required for all components that conform to the ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2. They are a set of eight registers, listed in register number order in the following table.

Table 10-18 Summary of the External Debug Peripheral Identification Registers

Register Value Offset
EDPIDR4 0x04 0xFD0
EDPIDR5 0x00 0xFD4
EDPIDR6 0x00 0xFD8
EDPIDR7 0x00 0xFDC
EDPIDR0 0x08 0xFE0
EDPIDR1 0xBD 0xFE4
EDPIDR2 0x0B 0xFE8
EDPIDR3 0x00 0xFEC
Only bits[7:0] of each External Debug Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight External Debug Peripheral ID Registers define a single 64-bit Peripheral ID.
The External Debug Peripheral ID registers are:

External Debug Peripheral Identification Register 0

The EDPIDR0 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDPIDR0 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDPIDR0 bit assignments.
Figure 10-14 EDPIDR0 bit assignments
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The following table shows the EDPIDR0 bit assignments.

Table 10-19 EDPIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:0] Part_0
0x08Least significant byte of the debug part number.

External Debug Peripheral Identification Register 1

The EDPIDR1 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDPIDR1 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDPIDR1 bit assignments.
Figure 10-15 EDPIDR1 bit assignments
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The following table shows the EDPIDR1 bit assignments.

Table 10-20 EDPIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] DES_0
0xBARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0xDMost significant nibble of the debug part number.

External Debug Peripheral Identification Register 2

The EDPIDR2 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDPIDR2 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDPIDR2 bit assignments.
Figure 10-16 EDPIDR2 bit assignments
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The following table shows the EDPIDR2 bit assignments.

Table 10-21 EDPIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Revision
0x0Part major revision.
[3] JEDEC
0b1RAO. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011ARM Limited. This is the most significant nibble of JEP106 ID code.

External Debug Peripheral Identification Register 3

The EDPIDR3 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDPIDR3 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDPIDR3 bit assignments.
Figure 10-17 EDPIDR3 bit assignments
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The following table shows the EDPIDR3 bit assignments.

Table 10-22 EDPIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] REVAND
0x0Part minor revision.
[3:0] CMOD
0x0Customer modified.

External Debug Peripheral Identification Register 4

The EDPIDR4 characteristics are:

Purpose
Provides information to identify an external debug component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 11-1 External register access conditions describes the access conditions.
Configurations
The EDPIDR4 is in the Debug power domain.
Attributes
See 10.7 Memory-mapped register summary.
The following figure shows the EDPIDR4 bit assignments.
Figure 10-18 EDPIDR4 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the EDPIDR4 bit assignments.

Table 10-23 EDPIDR4 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Size
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
[3:0] DES_2
0x4ARM Limited. This is the least significant nibble JEP106 continuation code.

External Debug Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0.

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