ARM Cortex-A72 MPCore Processor Technical Reference Manual : 4.3.50 Exception Syndrome Register, EL1 and EL3

4.3.50 Exception Syndrome Register, EL1 and EL3

The ESR_EL1 and ESR_EL3 characteristics are:

Purpose

ESR_EL1 holds syndrome information for an exception taken to EL1.

ESR_EL3 holds syndrome information for an exception taken to EL3.

Usage constraints

The accessibility to the ESR_EL1 by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	RW	RW	RW	RW	RW

The accessibility to the ESR_EL3 by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	-	-	-	RW	RW

Configurations

The ESR_EL1 is architecturally mapped to the Non-secure AArch32 DFSR register.

The ESR_EL3 is mapped to the Secure AArch32 DFSR register.

Attributes

See the register summary in Table 4-2 AArch64 exception handling registers.

EC==0b100000 and EC==0b100001, Instruction Aborts

This section describes the IMPLEMENTATION DEFINED behavior of the EA bit for Instruction Abort exceptions.

The following figure shows the ESR_EL1 and ESR_EL3 bit assignments for the Instruction Abort exception classes, that is, when EC==0b100000 or EC==0b100001.

Figure 4-44 ESR_EL1 and ESR_EL3 bit assignments

The following table shows the ESR_EL1 and ESR_EL3 bit assignments for the Instruction Abort exception class.

Table 4-60 ESR_EL1 and ESR_EL3 bit assignments

Bits Name Function

[31:26]

Exception Class:

`0b100000`	Instruction Abort that caused entry from a lower Exception level in AArch32 or AArch64.
`0b100001`	Instruction Abort that caused entry from a current Exception level in AArch64.

[25] IL Instruction Length for synchronous exceptions.

[24:10] - Reserved, RES0.

[9]

External abort type. This bit indicates whether an AXI decode or slave error caused an abort. The possible values are:

0	External abort marked as DECERR.
1	External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[8] - Reserved, RES0.

[7] S1PTW When 1, indicates the instruction fault came from a second stage fault during a first stage translation table walk.

[6] - Reserved, RES0.

[5:0]

IFSC

Instruction Fault Status Code. This field indicates the type of exception generated. The possible values are:

`0b000000`	Address size fault in TTBR0 or TTBR1.
`0b000101`	Translation fault, 1st level.
`00b00110`	Translation fault, 2nd level.
`00b00111`	Translation fault, 3rd level.
`0b001001`	Access flag fault, 1st level.
`0b001010`	Access flag fault, 2nd level.
`0b001011`	Access flag fault, 3rd level.
`0b001101`	Permission fault, 1st level.
`0b001110`	Permission fault, 2nd level.
`0b001111`	Permission fault, 3rd level.
`0b010000`	Synchronous external abort.
`0b011000`	Synchronous parity error on memory access.
`0b010101`	Synchronous external abort on translation table walk, 1st level.
`0b010110`	Synchronous external abort on translation table walk, 2nd level.
`0b010111`	Synchronous external abort on translation table walk, 3rd level.
`0b011101`	Synchronous parity error on memory access on translation table walk, 1st level.
`0b011110`	Synchronous parity error on memory access on translation table walk, 2nd level.
`0b011111`	Synchronous parity error on memory access on translation table walk, 3rd level.
`0b100001`	Alignment fault.
`0b100010`	Debug event.

All other values are reserved.

The lookup level associated with a fault is:

For a fault generated on a translation table walk, the lookup level of the walk being performed.
For a Translation fault, the lookup level of the translation table that gave the fault. If a fault occurs because an MMU is disabled, or because the input address is outside the range specified by the appropriate base address register or registers, the fault is reported as a First level fault.
For an Access flag fault, the lookup level of the translation table that gave the fault.
For a Permission fault, including a Permission fault cased by hierarchical permissions, the lookup level of the final level of translation table accessed for the translation. That is, the lookup level of the translation table that returned a Block or Page descriptor.

All exception classes except the Instruction Abort are architecturally defined in the ARM^® Architecture Reference Manual ARMv8. The SError Interrupt exception classes are architecturally defined in the ARM^® Generic Interrupt Controller Architecture Specification, GICv3 with the exception of four bits.

The following changes are Cortex-A72 implementation-defined and only apply to SError Interrupt exception classes.

Table 4-61 ESR_EL1 and ESR_EL3 Cortex-A72 implementation-defined SError Interrupt exception classes bit assignments

Bits Name Function

[15]

Unattributable System Error

`0b1`	Unattributable - cannot be attributed to the processing element counting the event.
`0b0`	Attributable - can be attributed to the processing element counting the event.

[14]

Uncontainable System Error

`0b1`	Uncontainable – an event which cannot be contained to a particular code sequence.
`0b0`	Containable - an Attributable event which can be contained to a particular code sequence.

[1:0]

System Error Source

`0b00`	Decode error
`0b01`	ECC error
`0b10`	Slave error
`0b11`	Reserved

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