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This section describes the following dynamic power management features in the processor:
Wait for Interrupt (WFI) is a feature of the ARMv8-A architecture that puts the core in a low-power state by disabling the clocks in the core while keeping the core powered up. This reduces the power drawn to the static leakage when the core is in WFI low-power state.
WFIinstruction, the core waits for all instructions in the core to retire before entering the idle or low-power state. The
WFIinstruction ensures that all explicit memory accesses occurred before the
WFIinstruction in program order, have retired. For example, the
WFIinstruction ensures that the following instructions receive the required data or responses from the L2 memory system:
WFIinstruction ensures that store instructions update the cache or are issued to the L2 memory system.
Wait for Event (WFE) is a feature of the ARMv8-A architecture that uses a locking mechanism based on events to put the core in a low-power state by disabling the clocks in the core while keeping the core powered up. This reduces the power drawn to the static leakage current, when the core is in WFE low-power state.
WFEinstruction. When executing the
WFEinstruction, the core waits for all instructions in the core to complete before entering the idle or low-power state. The
WFEinstruction ensures that all explicit memory accesses occurred before the
WFEinstruction in program order, have completed.
The EVENTI signal enables an external agent to participate in the WFE and SEV event communication. When this signal is asserted, it sends an event message to all the cores in the processor. This is similar to executing an
SEV instruction on one core in the processor. This enables the external agent to signal to the core that it has released a semaphore and that the core can leave the WFE low-power state. The EVENTI input signal must remain HIGH for at least one CLK cycle to be visible by the cores.
SEVinstruction by checking the EVENTO signal. When any of the cores in the processor executes an
SEVinstruction, an event is signaled to all the cores in the processor, and the EVENTO signal is asserted. This signal is asserted HIGH for three CLK cycles when any of the cores executes an
The CLREXMONREQ signal has a corresponding CLREXMONACK response signal. This forms a standard 2-wire, 4-phase handshake that can be used to signal across the voltage and frequency boundary between the core and system.
When all the cores are in WFI low-power state, the shared L2 memory system logic that is common to all the cores can also enter a WFI low-power state.
The processor provides an efficient way to fully clean and invalidate the L2 cache in preparation for powering it down without requiring the waking of a core to perform the clean and invalidate through software.
ISBinstruction to ensure the CPU Extended Control Register and CPU Auxiliary Control Register writes are complete.
DSBinstruction to ensure completion of any prior prefetch requests.
When a core is in WFI low-power state or WFE low-power state, the clocks to the core are stopped. During these low-power states, the core might start the clocks for short periods of time to allow it to handle snoops or other short events but it remains in the low-power state.
WFIinstruction. The clocks in the core are stopped and STANDBYWFI is asserted. After the programmed number of Generic Timer CNTVALUEB ticks specified by CPUECTLR[2:0] field has elapsed, the CPUQACTIVE for that core is deasserted. This hints that retention is possible for that core.
As cores generally only stay in WFE low-power state for a short period of time, ARM recommends that you only take a core into retention when it is in WFI low-power state.
0b000, all assertions of CPUQREQn LOW receive CPUQDENY responses.
L2 RAM dynamic retention mode provides a way of saving power in an idle processor while allowing quick wake-up to service a snoop from ACE or CHI. The core supports dynamic retention of the L2 Data, Dirty, Tag, Inclusion PLRU, and Snoop Tag RAMs.
0b000, all assertions of L2QREQn LOW receive L2QDENY responses.
The processor supports dynamic high-level clock gating of the Advanced SIMD and FP unit to reduce dynamic power dissipation.
The processor supports dynamic high-level clock gating of the shared L2 control logic and the two L2 tag banks to reduce dynamic power dissipation.
In addition to extensive local clock gating to register flops, you can configure the processor to include Regional Clock Gates (RCGs) that can perform additional clock gating of logic blocks such as the register banks to reduce dynamic power dissipation.