The ICC_AP1R0_EL1 characteristics are:
- Provides support for preserving and restoring state in power-management
- Usage constraints
- This register is Banked to provide Secure and Non-secure copies. This ensures that
Non-secure accesses do not interfere with Secure operation. Accessibility and
constraints on this register are described in the ARM®
Generic Interrupt Controller Architecture Specification, GICv3.
- Available if the GIC is implemented for System register mode.
- See the register summary in Table 8-4 AArch64 GIC CPU interface System register summary.
The multiprocessor implements the ICC_AP1R0_EL1 according to the recommendations described
in the ARM® Generic Interrupt Controller Architecture
The following table shows the Cortex-A72 processor ICC_AP1R0_EL1
Table 8-8 Active Priority Group1 Register implementation
|Number of group priority bits
||Minimum legal value of Secure BPR
||Minimum legal value of Non-secure BPR
||Active Priority Group1 Registers implemented