ARM Cortex-A72 MPCore Processor Technical Reference Manual : 8.3.2 CPU interface memory-mapped register descriptions

8.3.2 CPU interface memory-mapped register descriptions

This section only describes registers whose implementation is specific to the Cortex-A72 processor. All other registers are described in the ARM^® Generic Interrupt Controller Architecture Specification, GICv3. Table 8-2 GIC CPU interface memory-mapped register summary provides cross-references to individual registers.

Active Priority Register

The GICC_APR0 characteristics are:

Purpose: Provides support for preserving and restoring state in power-management applications.
Usage constraints: This register is Banked to provide Secure and Non-secure copies. This ensures that Non-secure accesses do not interfere with Secure operation.
Configurations: Available if the GIC is implemented and setup for memory-mapped accesses.
Attributes: See the register summary in Table 8-2 GIC CPU interface memory-mapped register summary.

The processor implements the GICC_APR0 according to the recommendations described in the ARM^® Generic Interrupt Controller Architecture Specification, GICv3.

The following table shows the Cortex-A72 processor GICC_APR0 implementation.

Table 8-5 Active Priority Register implementation

Number of group priority bits	Preemption levels	Minimum legal value of Secure GICC_BPR	Minimum legal value of Non-secure GICC_BPR	Active Priority Registers implemented	View of Active Priority Registers for Non-secure accesses
5	32	2	3	GICC_APR0[31:0]	GICC_NSAPR0[31:16] appears as GICC_APR0[15:0]

Non-secure Active Priority Register

The GICC_NSAPR0 characteristics are:

Purpose: Provides support for preserving and restoring state in power-management applications.
Usage constraints: This register is only accessible from a Secure access.
Configurations: Available if the GIC is implemented.
Attributes: See the register summary in Table 8-2 GIC CPU interface memory-mapped register summary.

The processor implements the GICC_NSAPR0 according to the recommendations described in the ARM^® Generic Interrupt Controller Architecture Specification, GICv3. It is consistent with the GICC_APR0 Register.

CPU Interface Identification Register

The GICC_IIDR characteristics are:

Purpose: Provides information about the implementer and revision of the CPU interface.
Usage constraints.: There are no usage constraints.
Configurations: Available if the GIC is implemented.
Attributes: See the register summary in Table 8-2 GIC CPU interface memory-mapped register summary.

The following figure shows the GICC_IIDR bit assignments.

Figure 8-1 GICC_IIDR bit assignments

The following table shows the GICC_IIDR bit assignments.

Table 8-6 GICC_IIDR bit assignments

Bit Name Function

[31:20]

ProductID

Identifies the product:

0x008 Product ID.

[19:16]

Architecture version

Identifies the architecture version of the GIC:

0x4 Version 4.

[15:12]

Revision

Identifies the revision number for the CPU interface:

0x0 Revision 0.

[11:0]

Implementer

Contains the JEP106 code of the company that implemented the CPU interface. For an ARM implementation, these values are:

Bits[11:8] = `0x4`	The JEP106 continuation code of the implementer.
Bit[7]	Always 0.
Bits[6:0] = `0x3B`	The JEP106 identity code of the implementer.

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