The GICC_APR0 characteristics are:
- Purpose
- Provides support for preserving and restoring state in power-management
applications.
- Usage constraints
- This register is Banked to provide Secure and Non-secure copies. This ensures that
Non-secure accesses do not interfere with Secure operation.
- Configurations
- Available if the GIC is implemented and setup for memory-mapped accesses.
- Attributes
- See the register summary in Table 8-2 GIC CPU interface memory-mapped register summary.
The
processor
implements the GICC_APR0 according to the recommendations described in the ARM® Generic Interrupt Controller Architecture Specification,
GICv3.
The following table shows the Cortex-A72 processor GICC_APR0
implementation.
Table 8-5 Active Priority Register implementation
Number of group priority bits |
Preemption levels |
Minimum legal value of Secure GICC_BPR |
Minimum legal value of Non-secure GICC_BPR |
Active Priority Registers implemented |
View of Active Priority Registers for Non-secure accesses |
5 |
32 |
2 |
3 |
GICC_APR0[31:0] |
GICC_NSAPR0[31:16] appears as GICC_APR0[15:0] |