12.6.12 CTI Component Identification Registers

There are four read-only CTI Component Identification Registers, Component ID0 through Component ID3. The following table shows these registers.

Table 12-22 Summary of the CTI Component Identification Registers

Register Value Offset
CTICIDR0 0x0D 0xFF0
CTICIDR1 0x90 0xFF4
CTICIDR2 0x05 0xFF8
CTICIDR3 0xB1 0xFFC
The CTI Component ID registers are:

CTI Component Identification Register 0

The CTICIDR0 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTICIDR0 is in the Debug power domain.
CTICIDR0 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTICIDR0 bit assignments.
Figure 12-17 CTICIDR0 bit assignments
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The following table shows the CTICIDR0 bit assignments.

Table 12-23 CTICIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_0
0x0DPreamble byte 0

CTI Component Identification Register 1

The CTICIDR1 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTICIDR1 is in the Debug power domain.
CTICIDR1 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTICIDR1 bit assignments.
Figure 12-18 CTICIDR1 bit assignments
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The following table shows the CTICIDR1 bit assignments.

Table 12-24 CTICIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:4] CLASS
0x9Debug component
[3:0] PRMBL_1
0x0Preamble

CTI Component Identification Register 2

The CTICIDR2 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTICIDR2 is in the Debug power domain.
CTICIDR2 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTICIDR2 bit assignments.
Figure 12-19 CTICIDR2 bit assignments
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The following table shows the CTICIDR2 bit assignments.

Table 12-25 CTICIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_2
0x05Preamble byte 2

CTI Component Identification Register 3

The CTICIDR3 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTICIDR3 is in the Debug power domain.
CTICIDR3 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTICIDR3 bit assignments.
Figure 12-20 CTICIDR3 bit assignments
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The following table shows the CTICIDR3 bit assignments.

Table 12-26 CTICIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] PRMBL_3
0xB1Preamble byte 3
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