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12.6.11 CTI Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM CoreSight architecture. There is a set of eight registers, listed in register number order in the following table.

Table 12-16 Summary of the CTI Peripheral Identification Registers

Register Value Offset
CTIPIDR4 0x04 0xFD0
CTIPIDR5 0x00 0xFD4
CTIPIDR6 0x00 0xFD8
CTIPIDR7 0x00 0xFDC
CTIPIDR0 0x06 0xFE0
CTIPIDR1 0xB9 0xFE4
CTIPIDR2 0x4B 0xFE8
CTIPIDR3 0x00 0xFEC
Only bits[7:0] of each CTI Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight CTI Peripheral ID Registers define a single 64-bit Peripheral ID.
The CTI Peripheral ID registers are:

CTI Peripheral Identification Register 0

The CTIPIDR0 characteristics are:

PurposeProvides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTIPIDR0 is in the Debug power domain.
CTIPIDR0 is optional to implement in the external register interface.
AttributesSee 12.5 Cross trigger register summary.
The following figure shows the CTIPIDR0 bit assignments.
Figure 12-12 CTIPIDR0 bit assignments
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The following table shows the CTIPIDR0 bit assignments.

Table 12-17 CTIPIDR0 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:0] Part_0
0x06Least significant byte of the cross trigger part number

CTI Peripheral Identification Register 1

The CTIPIDR1 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTIPIDR1 is in the Debug power domain.
CTIPIDR1 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTIPIDR1 bit assignments.
Figure 12-13 CTIPIDR1 bit assignments
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The following table shows the CTIPIDR1 bit assignments.

Table 12-18 CTIPIDR1 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] DES_0
0xBARM Limited. This is the least significant nibble of JEP106 ID code.
[3:0] Part_1
0x9Most significant nibble of the cross trigger interface part number.

CTI Peripheral Identification Register 2

The CTIPIDR2 characteristics are:

PurposeProvides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTIPIDR2 is in the Debug power domain.
CTIPIDR2 is optional to implement in the external register interface.
AttributesSee 12.5 Cross trigger register summary.
The following figure shows the CTIPIDR2 bit assignments.
Figure 12-14 CTIPIDR2 bit assignments
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The following table shows the CTIPIDR2 bit assignments.

Table 12-19 CTI PIDR2 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Revision
0x4Part major revision.
[3] JEDEC
0b1RES1. Indicates a JEP106 identity code is used.
[2:0] DES_1
0b011ARM Limited. This is the most significant nibble of JEP106 ID code.

CTI Peripheral Identification Register 3

The CTIPIDR3 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTIPIDR3 is in the Debug power domain.
CTIPIDR3 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTIPIDR3 bit assignments.
Figure 12-15 CTIPIDR3 bit assignments
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The following table shows the CTIPIDR3 bit assignments.

Table 12-20 CTIPIDR3 bit assignments

Bits Name Function
[31:8] - Reserved, RES0
[7:4] REVAND
0x0Part minor revision
[3:0] CMOD
0x0Customer modified

CTI Peripheral Identification Register 4

The CTIPIDR4 characteristics are:

Purpose
Provides information to identify a CTI component.
Usage constraints
Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 12-3 Cross trigger register summary describes the access conditions.
Configurations
CTIPIDR4 is in the Debug power domain.
CTIPIDR4 is optional to implement in the external register interface.
Attributes
See 12.5 Cross trigger register summary.
The following figure shows the CTIPIDR4 bit assignments.
Figure 12-16 CTIPIDR4 bit assignments
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The following table shows the CTIPIDR4 bit assignments.

Table 12-21 CTIPIDR4 bit assignments

Bits Name Function
[31:8] - Reserved, RES0.
[7:4] Size
0x0Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers.
[3:0] DES_2
0x4ARM Limited. This is the least significant nibble JEP106 continuation code.

CTI Peripheral Identification Register 5-7

No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0.

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