4.3.54 Exception Syndrome Register, EL2

The ESR_EL2 characteristics are:
PurposeHolds syndrome information for an exception taken to EL2.
Usage constraints
The accessibility to the ESR_EL2 in AArch64 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW RW
The accessibility to the HSR in AArch32 state by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - RW RW -
Configurations
The ESR_EL2 is:
  • A Banked EL2 register.
  • Architecturally mapped to the AArch32 HSR register.
AttributesSee the register summary in Table 4-2 AArch64 exception handling registers.
The following figure shows the ESR_EL2 bit assignments.
Figure 4-47 ESR_EL2 bit assignments
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The following table shows the ESR_EL2 bit assignments.

Table 4-65 ESR_EL2 bit assignments

Bits Name Function
[31:26] EC
Exception class. The exception class for the exception that is taken in Hyp mode.
When zero, this field indicates that the reason for the exception is not known. In this case, the other fields in this register are UNKNOWN. Otherwise, the field holds the exception class for the exception. See the ARM® Architecture Reference Manual ARMv8 for more information.
[25] IL
Instruction length. Indicates the size of the instruction that has been trapped to Hyp mode. The values are:
016-bit instruction.
132-bit instruction.
This field is not valid for:
  • Instruction Aborts.
  • Data Aborts that do not have ISS information, or for which the ISS is not valid.
In these cases the field is RES0.
[24:0] ISS Instruction specific syndrome. The interpretation of this field depends on the value of the EC field. See Encoding of ISS[24:20] when HSR[31:30] is 0b00>.
All exception classes except the Instruction Abort are architecturally defined in the ARM® Architecture Reference Manual ARMv8. The SError Interrupt exception classes are architecturally defined in the ARM® Generic Interrupt Controller Architecture Specification, GICv3 with the exception of four bits.
The following changes are Cortex-A72 implementation-defined and only apply to SError Interrupt exception classes.

Table 4-66 ESR_EL2 Cortex-A72 implementation-defined SError Interrupt exception classes bit assignments

Bits Name Function
[15] Unattributable System Error
0b1Unattributable - cannot be attributed to the processing element counting the event.
0b0Attributable - can be attributed to the processing element counting the event.
[14] Uncontainable System Error
0b1Uncontainable – an event which cannot be contained to a particular code sequence.
0b0Containable - an Attributable event which can be contained to a particular code sequence.
[1:0] System Error Source
0b00Decode error
0b01ECC error
0b10Slave error
0b11Reserved

Encoding of ISS[24:20] when HSR[31:30] is 0b00

For EC values that are nonzero and have the two most-significant bits 0b00, ISS[24:20] provides the condition field for the trapped instruction, together with a valid flag for this field. The encoding of this part of the ISS field is:
CV, ISS[24]
Condition valid. Possible values of this bit are:
0The COND field is not valid.
1The COND field is valid.
When an instruction is trapped, CV is set to 1.
COND, ISS[23:20]
The Condition field for the trapped instruction. This field is valid only when CV is set to 1.
If CV is set to 0, this field is UNK/RES0.
When an instruction is trapped, the COND field is 0xE.
To access the ESR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, ESR_EL2; Read EL2 Exception Syndrome Register
MSR ESR_EL2, <Xt>; Write EL2 Exception Syndrome Register
To access the HSR in AArch32 state, read or write the CP15 register with:
MRC p15, 4, <Rt>, c5, c1, 0; Read Hyp Syndrome Register
MCR p15, 4, <Rt>, c5, c1, 0; Write Hyp Syndrome Register
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