13.8.1 Interaction with the Performance Monitor Unit

The Cortex-A72 processor includes a Performance Monitor Unit (PMU) that enables events, such as cache misses and instructions executed, to be counted over a period of time. This section describes how the PMU and ETM function together.
Related information
Chapter 11 Performance Monitor Unit

Use of PMU events by the ETM

All PMU architectural events are available to the ETM through the extended input facility. See the ARM® Architectural Reference Manual ARMv8 for more information about PMU events.
The ETM uses four extended external input selectors to access the PMU events. Each selector can independently select one of the PMU events, that are then active for the cycles where the relevant events occur. These selected events can then be accessed by any of the event registers within the ETM.
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