About this book

This document describes the ARM® Cortex®-A72 processor.

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.

Intended audience

This document is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the Cortex-A72 processor.

Using this book

This book is organized into the following chapters:
Chapter 1 Introduction

This chapter introduces the Cortex-A72 processor and its features.

Chapter 2 Functional Description

This chapter describes the functionality of the Cortex-A72 processor.

Chapter 3 Programmers Model

This chapter describes the processor registers and provides information for programming the processor.

Chapter 4 System Control

This chapter describes the System registers, their structure, operation, and how to use them.

Chapter 5 Memory Management Unit

This section describes the Memory Management Unit (MMU).

Chapter 6 Level 1 Memory System

This section describes the Level 1 (L1) memory system.

Chapter 7 Level 2 Memory System

This chapter describes the Level 2 (L2) memory system.

Chapter 8 Generic Interrupt Controller CPU Interface

This section describes the Cortex-A72 processor implementation of the GIC CPU interface.

Chapter 9 Generic Timer

This chapter describes the Cortex-A72 processor implementation of the ARM Generic Timer.

Chapter 10 Debug

This section describes the Cortex-A72 processor debug registers and shows examples of how to use them.

Chapter 11 Performance Monitor Unit

This section describes the Performance Monitor Unit (PMU) and the registers that it uses.

Chapter 12 Cross Trigger

This chapter describes the cross trigger interfaces for the Cortex-A72 processor.

Chapter 13 Embedded Trace Macrocell

This section describes the Embedded Trace Macrocell (ETM) for the Cortex-A72 processor.

Chapter 14 Advanced SIMD and Floating-point

This chapter describes the Advanced SIMD and Floating-point features and registers in the Cortex-A72 processor.

Appendix A Signal Descriptions

This section describes the Cortex-A72 processor signals.

Appendix B AArch32 Unpredictable Behaviors

This appendix describes specific Cortex-A72 processor UNPREDICTABLE behaviors that are of particular interest.

Appendix C Revisions

This appendix describes the technical changes between released issues of this book.

The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
Introduces special terminology, denotes cross-references, and citations.
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
Figure 1 Key to timing diagram conventions
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The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
  • HIGH for active-HIGH signals.
  • LOW for active-LOW signals.
Lower-case n
At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.
ARM publications
  • ARM® AMBA® APB Protocol Specification (ARM IHI 0024).
  • ARM® AMBA® 3 ATB Protocol Specification (ARM IHI 0032).
  • ARM® AMBA® AXI and ACE Protocol Specification (ARM IHI 0022).
  • ARM® AMBA® AXI4-Stream Protocol Specification (ARM IHI 0051).
  • ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (ARM DDI 0487).
  • ARM® CoreSight™ SoC-400 Technical Reference Manual (ARM DII 0480).
  • ARM® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 (ARM IHI 0031).
  • ARM® Embedded Trace Macrocell Architecture Specification, ETMv4 (ARM IHI 0064).
  • ARM® Generic Interrupt Controller Architecture Specification GICv3 (ARM IHI 0048).
The following confidential books are only available to licensees:
  • ARM® CoreSight™ Architecture Specification (ARM IHI 0029).
  • ARM® AMBA® 5 CHI Protocol Specification (ARM IHI 0050).
  • ARM® Cortex-A72 MPCore Processor Configuration and Sign-off Guide (ARM 100098).
  • ARM® Cortex-A72 MPCore Processor Integration Manual (ARM 100096).
  • ARM® Cortex-A72 MPCore Processor Cryptography Extension Technical Reference Manual (ARM 100097).
Other publications
  • ANSI/IEEE, IEEE Standard for Binary Floating-Point Arithmetic, Std 754-1985.
  • ANSI/IEEE, IEEE Standard for Floating-Point Arithmetic, Std 754-2008.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_04_en
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