The Cortex-A72 processor includes the following features:
- Full implementation of the ARMv8-A architecture profile. See 1.2 Compliance.
- Superscalar, variable-length, out-of-order pipeline.
- Dynamic branch prediction with Branch Target
Buffer (BTB) and Global History Buffer (GHB)
RAMs, a return stack, and an indirect predictor.
- 48-entry fully-associative L1 instruction Translation Lookaside Buffer (TLB) with native support for 4KB, 64KB, and
1MB page sizes.
- 32-entry fully-associative L1 data TLB with native support for 4KB,
64KB, and 1MB page sizes.
- 4-way set-associative unified 1024-entry Level
2 (L2) TLB in each processor.
- Fixed 48K L1 instruction cache and 32K L1 data cache.
- Shared L2 cache of 512KB, 1MB,
2MB or 4MB configurable size.
- Optional Error Correction Code (ECC)
protection for L2 cache, and optional ECC protection for L1 data
cache and parity protection for L1 instruction cache.
- AMBA 4 AXI Coherency Extensions (ACE)
or CHI master interface.
- Optional Accelerator Coherency Port (ACP)
implemented as an AXI4 slave interface.
Embedded Trace Macrocell (ETM) based on the ETMv4
Performance Monitor Unit (PMU) support based on the
Cross Trigger Interface (CTI) for multiprocessor
- Optional Cryptography engine.
Optional Generic Interrupt Controller (GIC) CPU interface.
- Support for power management with multiple power domains.
Note The optional Cryptography engine is not included in the
base product of the Cortex-A72 processor. ARM
requires licensees to have contractual rights to obtain the Cortex-A72 processor Cryptography engine.