2.2.1 Memory interface

The processor has a memory interface that implements either an AMBA 4 ACE or CHI bus interface:

  • ACE is an extension to the Advanced eXtensible Interface (AXI) protocol and provides the following enhancements:
    • Support for hardware cache coherency.
    • Barrier transactions that guarantee transaction ordering.
    • Distributed virtual memory messaging, enabling management of a virtual memory system.
    See the ARM® AMBA® AXI and ACE Protocol Specification for more information.
  • CHI is a protocol that provides an architecture for connecting multiple nodes using a scalable interconnect. The nodes on the interconnect might be cores, core clusters, I/O bridges, memory controllers, or graphics processors. See the ARM® AMBA® 5 CHI Protocol Specification.
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