The processor has a memory interface that implements either an AMBA 4 ACE or CHI bus interface:
ACE is an extension to the Advanced eXtensible Interface (AXI) protocol
and provides the following enhancements:
Support for hardware cache coherency.
Barrier transactions that guarantee transaction ordering.
Distributed virtual memory messaging, enabling management of a virtual memory
AXI and ACE Protocol Specification
for more information.
CHI is a protocol that provides an architecture for connecting multiple nodes using a
scalable interconnect. The nodes on the interconnect might be
clusters, I/O bridges, memory controllers, or graphics processors. See the
AMBA® 5 CHI Protocol Specification.