The L2 memory system also interfaces with an optional Accelerator Coherency Port (ACP)
that is implemented as an AXI slave interface.
The features of the L2 memory system include:
- Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
- Fixed line length of 64 bytes.
- Physically indexed and tagged cache.
- 16-way set-associative cache structure.
- Banked pipeline structures.
- Inclusion property with L1 data caches.
- Software-programmable pseudo-least-recently-used or
pseudo-random cache-replacement policy.
- Configurable 128-bit wide ACE or 128-bit wide CHI interface
with support for multiple outstanding requests.
- Optional 128-bit wide ACP with support for multiple incoming
requests.
- Duplicate copies of the L1 data cache directories for coherency
support.
- Configurable number of Fill/Eviction
Queue (FEQ) entries to 20, 24, or 28.
- Optional Error Correction Code
(ECC) support.
- Optional hardware prefetch support.
- Software-programmable variable latency RAMs.
- Register slice support for large L2 cache sizes to minimize
impact on routing delays.
- MBIST support.
Note
- The Cortex-A72
processor does not support TLB or cache lockdown.