ARM Cortex-A72 MPCore Processor Technical Reference Manual : 7.1 About the L2 memory system

7.1 About the L2 memory system

The L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting up to four cores within a cluster and a configurable coherent external interface supporting AMBA4 (ACE) or CHI architectures.

The L2 memory system also interfaces with an optional Accelerator Coherency Port (ACP) that is implemented as an AXI slave interface.

The features of the L2 memory system include:

Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.
Fixed line length of 64 bytes.
Physically indexed and tagged cache.
16-way set-associative cache structure.
Banked pipeline structures.
Inclusion property with L1 data caches.
Software-programmable pseudo-least-recently-used or pseudo-random cache-replacement policy.
Configurable 128-bit wide ACE or 128-bit wide CHI interface with support for multiple outstanding requests.
Optional 128-bit wide ACP with support for multiple incoming requests.
Duplicate copies of the L1 data cache directories for coherency support.
Configurable number of Fill/Eviction Queue (FEQ) entries to 20, 24, or 28.
Optional Error Correction Code (ECC) support.
Optional hardware prefetch support.
Software-programmable variable latency RAMs.
Register slice support for large L2 cache sizes to minimize impact on routing delays.
MBIST support.

Note

The Cortex-A72 processor does not support TLB or cache lockdown.

Related information

7.2.2 Strictly-enforced inclusion property with L1 data caches

7.2.4 Error Correction Code

7.2.5 Register slice support for large cache sizes

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